Intel ACPI Component Architecture ACPI Binary Table Extraction Utility version 20200925 Copyright (c) 2000 - 2020 Intel Corporation Signature Length Version Oem Oem Oem Compiler Compiler Id TableId RevisionId Name Revision _________ __________ ____ ________ __________ __________ _______ __________ 01) SSDT 0x000000A6 0x01 "APPLE " "Cpu1Tst " 0x00003000 "INTL" 0x20061109 02) MCFG 0x0000003C 0x01 "APPLE " "Apple00 " 0x00000001 "Loki" 0x0000005F 03) ASF! 0x000000A5 0x20 "APPLE " "Apple00 " 0x00000001 "Loki" 0x0000005F 04) APIC 0x00000068 0x01 "APPLE " "Apple00 " 0x00000001 "Loki" 0x0000005F 05) ECDT 0x00000053 0x01 "APPLE " "Apple00 " 0x00000001 "Loki" 0x0000005F 06) SSDT 0x000004DC 0x01 "APPLE " "CpuPm " 0x00003000 "INTL" 0x20061109 07) DSDT 0x00003DA8 0x01 "APPLE " "iMac " 0x00080001 "INTL" 0x20061109 08) SBST 0x00000030 0x01 "APPLE " "Apple00 " 0x00000001 "Loki" 0x0000005F 09) SSDT 0x0000025F 0x01 "APPLE " "Cpu0Tst " 0x00003000 "INTL" 0x20061109 10) FACP 0x000000F4 0x03 "APPLE " "Apple00 " 0x000000C1 "Loki" 0x0000005F 11) SSDT 0x00000137 0x01 "APPLE " "SataAhci" 0x00001000 "INTL" 0x20061109 12) HPET 0x00000038 0x01 "APPLE " "Apple00 " 0x00000001 "Loki" 0x0000005F 13) FACS 0x00000040 0x01 14) SSDT 0x000000C8 0x01 "APPLE " "Cpu1Ist " 0x00003000 "INTL" 0x20061109 15) SSDT 0x000002BC 0x01 "APPLE " "Cpu0Ist " 0x00003000 "INTL" 0x20061109 16) SSDT 0x00000085 0x01 "APPLE " "Cpu1Cst " 0x00003000 "INTL" 0x20061109 17) SSDT 0x0000028F 0x01 "APPLE " "Cpu0Cst " 0x00003001 "INTL" 0x20061109 Found 17 ACPI tables in /root/HW_PROBE/LATEST/24wUYhtGlP/hw.info/logs/acpidump APIC ---- [000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 4] Table Length : 00000068 [008h 0008 1] Revision : 01 [009h 0009 1] Checksum : 8E [00Ah 0010 6] Oem ID : "APPLE " [010h 0016 8] Oem Table ID : "Apple00" [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "Loki" [020h 0032 4] Asl Compiler Revision : 0000005F [024h 0036 4] Local Apic Address : FEE00000 [028h 0040 4] Flags (decoded below) : 00000001 PC-AT Compatibility : 1 [02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] [02Dh 0045 1] Length : 08 [02Eh 0046 1] Processor ID : 00 [02Fh 0047 1] Local Apic ID : 00 [030h 0048 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Runtime Online Capable : 0 [034h 0052 1] Subtable Type : 00 [Processor Local APIC] [035h 0053 1] Length : 08 [036h 0054 1] Processor ID : 01 [037h 0055 1] Local Apic ID : 01 [038h 0056 4] Flags (decoded below) : 00000001 Processor Enabled : 1 Runtime Online Capable : 0 [03Ch 0060 1] Subtable Type : 01 [I/O APIC] [03Dh 0061 1] Length : 0C [03Eh 0062 1] I/O Apic ID : 01 [03Fh 0063 1] Reserved : 00 [040h 0064 4] Address : FEC00000 [044h 0068 4] Interrupt : 00000000 [048h 0072 1] Subtable Type : 02 [Interrupt Source Override] [049h 0073 1] Length : 0A [04Ah 0074 1] Bus : 00 [04Bh 0075 1] Source : 00 [04Ch 0076 4] Interrupt : 00000002 [050h 0080 2] Flags (decoded below) : 0000 Polarity : 0 Trigger Mode : 0 [052h 0082 1] Subtable Type : 02 [Interrupt Source Override] [053h 0083 1] Length : 0A [054h 0084 1] Bus : 00 [055h 0085 1] Source : 09 [056h 0086 4] Interrupt : 00000009 [05Ah 0090 2] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 [05Ch 0092 1] Subtable Type : 04 [Local APIC NMI] [05Dh 0093 1] Length : 06 [05Eh 0094 1] Processor ID : 00 [05Fh 0095 2] Flags (decoded below) : 0005 Polarity : 1 Trigger Mode : 1 [061h 0097 1] Interrupt Input LINT : 01 [062h 0098 1] Subtable Type : 04 [Local APIC NMI] [063h 0099 1] Length : 06 [064h 0100 1] Processor ID : 01 [065h 0101 2] Flags (decoded below) : 0005 Polarity : 1 Trigger Mode : 1 [067h 0103 1] Interrupt Input LINT : 01 Raw Table Data: Length 104 (0x68) 0000: 41 50 49 43 68 00 00 00 01 8E 41 50 50 4C 45 20 // APICh.....APPLE 0010: 41 70 70 6C 65 30 30 00 01 00 00 00 4C 6F 6B 69 // Apple00.....Loki 0020: 5F 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // _............... 0030: 01 00 00 00 00 08 01 01 01 00 00 00 01 0C 01 00 // ................ 0040: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................ 0050: 00 00 02 0A 00 09 09 00 00 00 0D 00 04 06 00 05 // ................ 0060: 00 01 04 06 01 05 00 01 // ........ ASF! ---- [000h 0000 4] Signature : "ASF!" [Alert Standard Format table] [004h 0004 4] Table Length : 000000A5 [008h 0008 1] Revision : 20 [009h 0009 1] Checksum : B6 [00Ah 0010 6] Oem ID : "APPLE " [010h 0016 8] Oem Table ID : "Apple00" [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "Loki" [020h 0032 4] Asl Compiler Revision : 0000005F [024h 0036 1] Subtable Type : 00 [ASF Information] [025h 0037 1] Reserved : 00 [026h 0038 2] Length : 0010 [028h 0040 1] Minimum Reset Value : 05 [029h 0041 1] Minimum Polling Interval : FF [02Ah 0042 2] System ID : 0001 [02Ch 0044 4] Manufacturer ID : BE110000 [030h 0048 1] Flags : 00 [031h 0049 3] Reserved : 000000 [034h 0052 1] Subtable Type : 01 [ASF Alerts] [035h 0053 1] Reserved : 00 [036h 0054 2] Length : 002C [038h 0056 1] AssertMask : 00 [039h 0057 1] DeassertMask : 00 [03Ah 0058 1] Alert Count : 03 [03Bh 0059 1] Alert Data Length : 0C [03Ch 0060 1] Address : 89 [03Dh 0061 1] Command : 04 [03Eh 0062 1] Mask : 01 [03Fh 0063 1] Value : 01 [040h 0064 1] SensorType : 05 [041h 0065 1] Type : 6F [042h 0066 1] Offset : 00 [043h 0067 1] SourceType : 68 [044h 0068 1] Severity : 08 [045h 0069 1] SensorNumber : 88 [046h 0070 1] Entity : 17 [047h 0071 1] Instance : 00 [048h 0072 1] Address : 89 [049h 0073 1] Command : 04 [04Ah 0074 1] Mask : 04 [04Bh 0075 1] Value : 04 [04Ch 0076 1] SensorType : 07 [04Dh 0077 1] Type : 6F [04Eh 0078 1] Offset : 00 [04Fh 0079 1] SourceType : 68 [050h 0080 1] Severity : 20 [051h 0081 1] SensorNumber : 88 [052h 0082 1] Entity : 03 [053h 0083 1] Instance : 00 [054h 0084 1] Address : 89 [055h 0085 1] Command : 05 [056h 0086 1] Mask : 01 [057h 0087 1] Value : 01 [058h 0088 1] SensorType : 19 [059h 0089 1] Type : 6F [05Ah 0090 1] Offset : 00 [05Bh 0091 1] SourceType : 68 [05Ch 0092 1] Severity : 20 [05Dh 0093 1] SensorNumber : 88 [05Eh 0094 1] Entity : 22 [05Fh 0095 1] Instance : 00 [060h 0096 1] Subtable Type : 02 [ASF Remote Control] [061h 0097 1] Reserved : 00 [062h 0098 2] Length : 0018 [064h 0100 1] Control Count : 04 [065h 0101 1] Control Data Length : 04 [066h 0102 2] Reserved : 0000 [068h 0104 1] Function : 00 [069h 0105 1] Address : 88 [06Ah 0106 1] Command : 00 [06Bh 0107 1] Value : 03 [06Ch 0108 1] Function : 01 [06Dh 0109 1] Address : 88 [06Eh 0110 1] Command : 00 [06Fh 0111 1] Value : 02 [070h 0112 1] Function : 02 [071h 0113 1] Address : 88 [072h 0114 1] Command : 00 [073h 0115 1] Value : 01 [074h 0116 1] Function : 03 [075h 0117 1] Address : 88 [076h 0118 1] Command : 00 [077h 0119 1] Value : 04 [078h 0120 1] Subtable Type : 03 [ASF RMCP Boot Options] [079h 0121 1] Reserved : 00 [07Ah 0122 2] Length : 0017 [07Ch 0124 7] Capabilities : 20 F8 00 00 00 1F F0 [083h 0131 1] Completion Code : 00 [084h 0132 4] Enterprise ID : BE110000 [088h 0136 1] Command : 00 [089h 0137 2] Parameter : 0000 [08Bh 0139 2] Boot Options : 0100 [08Dh 0141 2] Oem Parameters : 0000 [08Fh 0143 1] Subtable Type : 84 [ASF Address] [090h 0144 1] Reserved : 00 [091h 0145 2] Length : 0016 [093h 0147 1] Eprom Address : 00 [094h 0148 1] Device Count : 10 [095h 0149 1] Addresses : 5C 68 88 C2 D2 DC A0 A2 A4 A6 C8 00 00 00 00 00 Raw Table Data: Length 165 (0xA5) 0000: 41 53 46 21 A5 00 00 00 20 B6 41 50 50 4C 45 20 // ASF!.... .APPLE 0010: 41 70 70 6C 65 30 30 00 01 00 00 00 4C 6F 6B 69 // Apple00.....Loki 0020: 5F 00 00 00 00 00 10 00 05 FF 01 00 00 00 11 BE // _............... 0030: 00 00 00 00 01 00 2C 00 00 00 03 0C 89 04 01 01 // ......,......... 0040: 05 6F 00 68 08 88 17 00 89 04 04 04 07 6F 00 68 // .o.h.........o.h 0050: 20 88 03 00 89 05 01 01 19 6F 00 68 20 88 22 00 // ........o.h .". 0060: 02 00 18 00 04 04 00 00 00 88 00 03 01 88 00 02 // ................ 0070: 02 88 00 01 03 88 00 04 03 00 17 00 20 F8 00 00 // ............ ... 0080: 00 1F F0 00 00 00 11 BE 00 00 00 00 01 00 00 84 // ................ 0090: 00 16 00 00 10 5C 68 88 C2 D2 DC A0 A2 A4 A6 C8 // .....\h......... 00A0: 00 00 00 00 00 // ..... DSDT ---- DefinitionBlock ("", "DSDT", 1, "APPLE ", "iMac", 0x00080001) { External (PDC0, UnknownObj) External (PDC1, UnknownObj) OperationRegion (PRT0, SystemIO, 0x80, 0x04) Field (PRT0, DWordAcc, Lock, Preserve) { P80H, 32 } OperationRegion (SPRT, SystemIO, 0xB2, 0x02) Field (SPRT, ByteAcc, Lock, Preserve) { SSMP, 8 } OperationRegion (S_IO, SystemIO, 0x0680, 0x11) Field (S_IO, ByteAcc, NoLock, Preserve) { PMS0, 8, PME0, 8, PMS1, 8, PMS2, 8, PMS3, 8, PME1, 8, PME2, 8, PME3, 8, SMS1, 8, SMS2, 8, SME1, 8, SME2, 8, RT10, 1, RT11, 1, , 1, RT13, 1, Offset (0x0E), RT30, 1, RT31, 1, RT32, 1, RT33, 1, RT34, 1, RT35, 1, RT36, 1, RT37, 1, Offset (0x10), DLPC, 1, CK33, 1, CK14, 1 } OperationRegion (IO_T, SystemIO, 0x4000, 0x10) Field (IO_T, ByteAcc, NoLock, Preserve) { TRPI, 16, Offset (0x04), Offset (0x06), Offset (0x08), TRP0, 8, TRPC, 8, Offset (0x0B), Offset (0x0C), Offset (0x0D), Offset (0x0E), Offset (0x0F), Offset (0x10) } OperationRegion (IO_D, SystemIO, 0x0810, 0x08) Field (IO_D, ByteAcc, NoLock, Preserve) { TRPD, 8 } OperationRegion (PMIO, SystemIO, 0x0400, 0x80) Field (PMIO, ByteAcc, NoLock, Preserve) { Offset (0x28), , 2, SPST, 1, Offset (0x42), , 1, GPEC, 1 } OperationRegion (GNVS, SystemMemory, 0xBFED5A98, 0x0100) Field (GNVS, AnyAcc, Lock, Preserve) { OSYS, 16, SMIF, 8, PRM0, 8, PRM1, 8, SCIF, 8, PRM2, 8, PRM3, 8, LCKF, 8, PRM4, 8, PRM5, 8, P80D, 32, LIDS, 8, PWRS, 8, DBGS, 8, LINX, 8, Offset (0x14), ACTT, 8, PSVT, 8, TC1V, 8, TC2V, 8, TSPV, 8, CRTT, 8, DTSE, 8, DTS1, 8, DTS2, 8, DTSF, 8, BNUM, 8, B0SC, 8, B1SC, 8, B2SC, 8, B0SS, 8, B1SS, 8, B2SS, 8, Offset (0x28), APIC, 8, MPEN, 8, PCP0, 8, PCP1, 8, PPCM, 8, PPMF, 32, Offset (0x32), NATP, 8, CMAP, 8, CMBP, 8, LPTP, 8, FDCP, 8, CMCP, 8, CIRP, 8, Offset (0x3C), IGDS, 8, TLST, 8, CADL, 8, PADL, 8, CSTE, 16, NSTE, 16, SSTE, 16, NDID, 8, DID1, 32, DID2, 32, DID3, 32, DID4, 32, DID5, 32, BDSP, 8, PTY1, 8, PTY2, 8, PSCL, 8, TVF1, 8, TVF2, 8, Offset (0x63), GOPB, 32, BLCS, 8, BRTL, 8, ALSE, 8, ALAF, 8, LLOW, 8, LHIH, 8, Offset (0x6E), EMAE, 8, EMAP, 16, EMAL, 16, Offset (0x74), MEFE, 8, Offset (0x82), GTF0, 56, GTF2, 56, IDEM, 8, GTF1, 56 } OperationRegion (RCRB, SystemMemory, 0xFED1C000, 0x4000) Field (RCRB, DWordAcc, Lock, Preserve) { Offset (0x1000), Offset (0x3000), Offset (0x3404), HPAS, 2, , 5, HPAE, 1, Offset (0x3418), , 1, PATD, 1, SATD, 1, SMBD, 1, HDAD, 1, Offset (0x341A), RP1D, 1, RP2D, 1, RP3D, 1, RP4D, 1, RP5D, 1, RP6D, 1 } OperationRegion (GPIO, SystemIO, 0x0500, 0x3C) Field (GPIO, ByteAcc, NoLock, Preserve) { GU00, 8, GU01, 8, GU02, 8, GU03, 8, GIO0, 8, GIO1, 8, GIO2, 8, GIO3, 8, Offset (0x0C), , 2, GP2, 1, , 1, GP4, 1, GP5, 1, Offset (0x0D), , 1, GP9, 1, , 7, GP17, 1, , 5, GP23, 1, , 3, GP27, 1, , 1, GP29, 1, Offset (0x10), Offset (0x18), GB00, 8, GB01, 8, GB02, 8, GB03, 8, Offset (0x2C), , 2, GPI2, 1, , 1, GPI4, 1, Offset (0x2D), GIV1, 8, GIV2, 8, GIV3, 8, GU04, 8, GU05, 8, GU06, 8, GU07, 8, GIO4, 8, GIO5, 8, , 6, GD54, 1, Offset (0x37), GIO7, 8, , 5, GP37, 1, GP38, 1, Offset (0x39), GP40, 1, GL05, 7, , 6, GP54, 1, Offset (0x3B), GL07, 8 } Mutex (MUTX, 0x00) Scope (\_PR) { Processor (CPU0, 0x00, 0x00000410, 0x06) {} Processor (CPU1, 0x01, 0x00000410, 0x06) {} } Name (\DSEN, 0x01) Name (\ECON, 0x00) Name (\GPIC, 0x00) Name (\CTYP, 0x00) Name (\VFN0, 0x00) Method (OSDW, 0, NotSerialized) { If ((OSYS == 0x2710)) { Return (0x01) } Else { Return (0x00) } } Method (PINI, 0, NotSerialized) { If (CondRefOf (_OSI, Local0)) { If (_OSI ("Darwin")) { OSYS = 0x2710 } ElseIf (_OSI ("Linux")) { OSYS = 0x03E8 } ElseIf (_OSI ("Windows 2001")) { OSYS = 0x07D1 } ElseIf (_OSI ("Windows 2001 SP1")) { OSYS = 0x07D1 } ElseIf (_OSI ("Windows 2001 SP2")) { OSYS = 0x07D2 } ElseIf (_OSI ("Windows 2006")) { OSYS = 0x07D6 } } Else { OSYS = 0x07D0 } } Method (\_PIC, 1, NotSerialized) // _PIC: Interrupt Model { GPIC = Arg0 } Method (DTGP, 5, NotSerialized) { If ((Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b") /* Unknown UUID */)) { If ((Arg1 == One)) { If ((Arg2 == Zero)) { Arg4 = Buffer (0x01) { 0x03 // . } Return (One) } If ((Arg2 == One)) { Return (One) } } } Arg4 = Buffer (0x01) { 0x00 // . } Return (Zero) } Name (_S0, Package (0x03) // _S0_: S0 System State { 0x00, 0x00, 0x00 }) Name (_S3, Package (0x03) // _S3_: S3 System State { 0x05, 0x05, 0x00 }) Name (_S4, Package (0x03) // _S4_: S4 System State { 0x06, 0x06, 0x00 }) Name (_S5, Package (0x03) // _S5_: S5 System State { 0x07, 0x07, 0x00 }) Method (_PTS, 1, NotSerialized) // _PTS: Prepare To Sleep { P80D = 0x00 P8XH (0x00, Arg0) \_SB.PCI0.LPCB.EC.ECSS = Arg0 GD54 &= 0x00 GP54 &= 0x00 GP5 |= 0x01 } Method (_WAK, 1, NotSerialized) // _WAK: Wake { P8XH (0x00, 0x00) \_SB.PCI0.LPCB.EC.ECSS = 0x00 If (OSDW ()) { \_SB.PCI0.SBUS.ENAB () } LIDS = \_SB.PCI0.LPCB.EC.LSTE PWRS = \_SB.PCI0.LPCB.EC.RPWR PNOT () Return (Package (0x02) { 0x00, 0x00 }) } Scope (\_GPE) { Method (_L01, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF { If (((RP4D == 0x00) && \_SB.PCI0.RP04.HPS4)) { Sleep (0x64) If (\_SB.PCI0.RP04.PDC4) { \_SB.PCI0.RP04.PDC4 = 0x01 \_SB.PCI0.RP04.HPS4 = 0x01 Notify (\_SB.PCI0.RP04, 0x00) // Bus Check } Else { \_SB.PCI0.RP04.HPS4 = 0x01 } } If (((RP5D == 0x00) && \_SB.PCI0.RP05.HPS5)) { Sleep (0x64) If (\_SB.PCI0.RP05.PDC5) { \_SB.PCI0.RP05.PDC5 = 0x01 \_SB.PCI0.RP05.HPS5 = 0x01 Notify (\_SB.PCI0.RP05, 0x00) // Bus Check } Else { \_SB.PCI0.RP05.HPS5 = 0x01 } } If (((RP6D == 0x00) && \_SB.PCI0.RP06.HPS6)) { Sleep (0x64) If (\_SB.PCI0.RP06.PDC6) { \_SB.PCI0.RP06.PDC6 = 0x01 \_SB.PCI0.RP06.HPS6 = 0x01 Notify (\_SB.PCI0.RP06, 0x00) // Bus Check } Else { \_SB.PCI0.RP06.HPS6 = 0x01 } } } Method (_L02, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF { GPEC = 0x00 } Method (_L03, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF { Notify (\_SB.PCI0.UHC1, 0x02) // Device Wake Notify (\_SB.PWRB, 0x02) // Device Wake } Method (_L04, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF { Notify (\_SB.PCI0.UHC2, 0x02) // Device Wake Notify (\_SB.PWRB, 0x02) // Device Wake } Method (_L0C, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF { Notify (\_SB.PCI0.UHC3, 0x02) // Device Wake Notify (\_SB.PWRB, 0x02) // Device Wake } Method (_L0E, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF { Notify (\_SB.PCI0.UHC4, 0x02) // Device Wake Notify (\_SB.PWRB, 0x02) // Device Wake } Method (_L05, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF { Notify (\_SB.PCI0.UHC5, 0x02) // Device Wake Notify (\_SB.PWRB, 0x02) // Device Wake } Method (_L07, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF { \_SB.PCI0.SBUS.HSTS = 0x20 } Method (_L09, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF { If (\_SB.PCI0.RP04.PSP4) { \_SB.PCI0.RP04.PSP4 = 0x01 \_SB.PCI0.RP04.PMS4 = 0x01 Notify (\_SB.PCI0.RP04, 0x02) // Device Wake } If (\_SB.PCI0.RP05.PSP5) { \_SB.PCI0.RP05.PSP5 = 0x01 \_SB.PCI0.RP05.PMS5 = 0x01 Notify (\_SB.PCI0.RP05, 0x02) // Device Wake } If (\_SB.PCI0.RP06.PSP6) { \_SB.PCI0.RP06.PSP6 = 0x01 \_SB.PCI0.RP06.PMS6 = 0x01 Notify (\_SB.PCI0.RP06, 0x02) // Device Wake } } Method (_L0D, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF { If (\_SB.PCI0.EHC1.PMES) { \_SB.PCI0.EHC1.PMES = 0x01 Notify (\_SB.PCI0.EHC1, 0x02) // Device Wake Notify (\_SB.PWRB, 0x02) // Device Wake } If (\_SB.PCI0.EHC2.PMES) { \_SB.PCI0.EHC2.PMES = 0x01 Notify (\_SB.PCI0.EHC2, 0x02) // Device Wake Notify (\_SB.PWRB, 0x02) // Device Wake } } Method (_L11, 0, NotSerialized) // _Lxx: Level-Triggered GPE, xx=0x00-0xFF { Notify (\_SB.PCI0.RP04.FRWR, 0x00) // Bus Check } } Method (P8XH, 2, Serialized) { If ((Arg0 == 0x00)) { P80D = ((P80D & 0xFFFFFF00) | Arg1) } If ((Arg0 == 0x01)) { P80D = ((P80D & 0xFFFF00FF) | (Arg1 << 0x08)) } If ((Arg0 == 0x02)) { P80D = ((P80D & 0xFF00FFFF) | (Arg1 << 0x10)) } If ((Arg0 == 0x03)) { P80D = ((P80D & 0x00FFFFFF) | (Arg1 << 0x18)) } P80H = P80D /* \P80D */ } Method (PNOT, 0, Serialized) { If (MPEN) { If ((PDC0 & 0x08)) { Notify (\_PR.CPU0, 0x80) // Performance Capability Change If ((PDC0 & 0x10)) { Sleep (0x64) Notify (\_PR.CPU0, 0x81) // C-State Change } } If ((PDC1 & 0x08)) { Notify (\_PR.CPU1, 0x80) // Performance Capability Change If ((PDC1 & 0x10)) { Sleep (0x64) Notify (\_PR.CPU1, 0x81) // C-State Change } } } Else { Notify (\_PR.CPU0, 0x80) // Performance Capability Change Sleep (0x64) Notify (\_PR.CPU0, 0x81) // C-State Change } } Method (TRAP, 2, Serialized) { SMIF = Arg1 If ((Arg0 == 0x01)) { TRP0 = 0x00 Return (SMIF) /* \SMIF */ } If ((Arg0 == 0x02)) { DTSF = Arg1 TRPD = 0x00 Return (DTSF) /* \DTSF */ } Return (0x01) } Method (GETP, 1, Serialized) { If (((Arg0 & 0x09) == 0x00)) { Return (0xFFFFFFFF) } If (((Arg0 & 0x09) == 0x08)) { Return (0x0384) } Local0 = ((Arg0 & 0x0300) >> 0x08) Local1 = ((Arg0 & 0x3000) >> 0x0C) Return ((0x1E * (0x09 - (Local0 + Local1)))) } Method (GDMA, 5, Serialized) { If (Arg0) { If ((Arg1 && Arg4)) { Return (0x14) } If ((Arg2 && Arg4)) { Return (((0x04 - Arg3) * 0x0F)) } Return (((0x04 - Arg3) * 0x1E)) } Return (0xFFFFFFFF) } Method (GETT, 1, Serialized) { Return ((0x1E * (0x09 - (((Arg0 >> 0x02) & 0x03 ) + (Arg0 & 0x03))))) } Method (GETF, 3, Serialized) { Name (TMPF, 0x00) If (Arg0) { TMPF |= 0x01 } If ((Arg2 & 0x02)) { TMPF |= 0x02 } If (Arg1) { TMPF |= 0x04 } If ((Arg2 & 0x20)) { TMPF |= 0x08 } If ((Arg2 & 0x4000)) { TMPF |= 0x10 } Return (TMPF) /* \GETF.TMPF */ } Method (SETP, 3, Serialized) { If ((Arg0 > 0xF0)) { Return (0x08) } Else { If ((Arg1 & 0x02)) { If (((Arg0 <= 0x78) && (Arg2 & 0x02))) { Return (0x2301) } If (((Arg0 <= 0xB4) && (Arg2 & 0x01))) { Return (0x2101) } } Return (0x1001) } } Method (SDMA, 1, Serialized) { If ((Arg0 <= 0x14)) { Return (0x01) } If ((Arg0 <= 0x1E)) { Return (0x02) } If ((Arg0 <= 0x2D)) { Return (0x01) } If ((Arg0 <= 0x3C)) { Return (0x02) } If ((Arg0 <= 0x5A)) { Return (0x01) } Return (0x00) } Method (SETT, 3, Serialized) { If ((Arg1 & 0x02)) { If (((Arg0 <= 0x78) && (Arg2 & 0x02))) { Return (0x0B) } If (((Arg0 <= 0xB4) && (Arg2 & 0x01))) { Return (0x09) } } Return (0x04) } Scope (\_SB) { Method (_INI, 0, NotSerialized) // _INI: Initialize { PINI () } Device (PNLF) { Name (_HID, EisaId ("APP0002")) // _HID: Hardware ID Name (_CID, "backlight") // _CID: Compatible ID Name (_UID, 0x0A) // _UID: Unique ID Name (_STA, 0x0B) // _STA: Status } Device (PWRB) { Name (_HID, EisaId ("PNP0C0C") /* Power Button Device */) // _HID: Hardware ID } Device (SLPB) { Name (_HID, EisaId ("PNP0C0E") /* Sleep Button Device */) // _HID: Hardware ID Name (_STA, 0x0B) // _STA: Status } Device (PCI0) { Method (_INI, 0, NotSerialized) // _INI: Initialize { If (OSDW ()) { \_SB.PCI0.SBUS.ENAB () } } Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State { Return (0x03) } Method (_S4D, 0, NotSerialized) // _S4D: S4 Device State { Return (0x03) } Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Device (MCHC) { Name (_ADR, 0x00) // _ADR: Address OperationRegion (HBUS, PCI_Config, 0x40, 0xC0) Field (HBUS, DWordAcc, NoLock, Preserve) { EPEN, 1, , 11, EPBR, 20, Offset (0x08), MHEN, 1, , 13, MHBR, 18, Offset (0x20), PXEN, 1, PXSZ, 2, , 23, PXBR, 6, Offset (0x28), DIEN, 1, , 11, DIBR, 20, Offset (0x30), IPEN, 1, , 11, IPBR, 20, Offset (0x50), , 4, PM0H, 2, Offset (0x51), PM1L, 2, , 2, PM1H, 2, Offset (0x52), PM2L, 2, , 2, PM2H, 2, Offset (0x53), PM3L, 2, , 2, PM3H, 2, Offset (0x54), PM4L, 2, , 2, PM4H, 2, Offset (0x55), PM5L, 2, , 2, PM5H, 2, Offset (0x56), PM6L, 2, , 2, PM6H, 2, Offset (0x57), , 7, HENA, 1, Offset (0x62), TUUD, 16, Offset (0x70), , 4, TLUD, 12 } } Name (BUF0, ResourceTemplate () { WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, // Granularity 0x0000, // Range Minimum 0x00FF, // Range Maximum 0x0000, // Translation Offset 0x0100, // Length ,, ) DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x00000000, // Granularity 0x00000000, // Range Minimum 0x00000CF7, // Range Maximum 0x00000000, // Translation Offset 0x00000CF8, // Length ,, , TypeStatic, DenseTranslation) IO (Decode16, 0x0CF8, // Range Minimum 0x0CF8, // Range Maximum 0x01, // Alignment 0x08, // Length ) DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x00000000, // Granularity 0x00000D00, // Range Minimum 0x0000FFFF, // Range Maximum 0x00000000, // Translation Offset 0x0000F300, // Length ,, , TypeStatic, DenseTranslation) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000A0000, // Range Minimum 0x000BFFFF, // Range Maximum 0x00000000, // Translation Offset 0x00020000, // Length ,, , AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000C0000, // Range Minimum 0x000C3FFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, _Y00, AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000C4000, // Range Minimum 0x000C7FFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, _Y01, AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000C8000, // Range Minimum 0x000CBFFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, _Y02, AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000CC000, // Range Minimum 0x000CFFFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, _Y03, AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000D0000, // Range Minimum 0x000D3FFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, _Y04, AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000D4000, // Range Minimum 0x000D7FFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, _Y05, AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000D8000, // Range Minimum 0x000DBFFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, _Y06, AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000DC000, // Range Minimum 0x000DFFFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, _Y07, AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000E0000, // Range Minimum 0x000E3FFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, _Y08, AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000E4000, // Range Minimum 0x000E7FFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, _Y09, AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000E8000, // Range Minimum 0x000EBFFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, _Y0A, AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000EC000, // Range Minimum 0x000EFFFF, // Range Maximum 0x00000000, // Translation Offset 0x00004000, // Length ,, _Y0B, AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x000F0000, // Range Minimum 0x000FFFFF, // Range Maximum 0x00000000, // Translation Offset 0x00010000, // Length ,, _Y0C, AddressRangeMemory, TypeStatic) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity 0x00000000, // Range Minimum 0xFEBFFFFF, // Range Maximum 0x00000000, // Translation Offset 0x00000000, // Length ,, _Y0D, AddressRangeMemory, TypeStatic) }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { If (^MCHC.PM1L) { CreateDWordField (BUF0, \_SB.PCI0._Y00._LEN, C0LN) // _LEN: Length C0LN = Zero } If ((^MCHC.PM1L == 0x01)) { CreateBitField (BUF0, \_SB.PCI0._Y00._RW, C0RW) // _RW_: Read-Write Status C0RW = Zero } If (^MCHC.PM1H) { CreateDWordField (BUF0, \_SB.PCI0._Y01._LEN, C4LN) // _LEN: Length C4LN = Zero } If ((^MCHC.PM1H == 0x01)) { CreateBitField (BUF0, \_SB.PCI0._Y01._RW, C4RW) // _RW_: Read-Write Status C4RW = Zero } If (^MCHC.PM2L) { CreateDWordField (BUF0, \_SB.PCI0._Y02._LEN, C8LN) // _LEN: Length C8LN = Zero } If ((^MCHC.PM2L == 0x01)) { CreateBitField (BUF0, \_SB.PCI0._Y02._RW, C8RW) // _RW_: Read-Write Status C8RW = Zero } If (^MCHC.PM2H) { CreateDWordField (BUF0, \_SB.PCI0._Y03._LEN, CCLN) // _LEN: Length CCLN = Zero } If ((^MCHC.PM2H == 0x01)) { CreateBitField (BUF0, \_SB.PCI0._Y03._RW, CCRW) // _RW_: Read-Write Status CCRW = Zero } If (^MCHC.PM3L) { CreateDWordField (BUF0, \_SB.PCI0._Y04._LEN, D0LN) // _LEN: Length D0LN = Zero } If ((^MCHC.PM3L == 0x01)) { CreateBitField (BUF0, \_SB.PCI0._Y04._RW, D0RW) // _RW_: Read-Write Status D0RW = Zero } If (^MCHC.PM3H) { CreateDWordField (BUF0, \_SB.PCI0._Y05._LEN, D4LN) // _LEN: Length D4LN = Zero } If ((^MCHC.PM3H == 0x01)) { CreateBitField (BUF0, \_SB.PCI0._Y05._RW, D4RW) // _RW_: Read-Write Status D4RW = Zero } If (^MCHC.PM4L) { CreateDWordField (BUF0, \_SB.PCI0._Y06._LEN, D8LN) // _LEN: Length D8LN = Zero } If ((^MCHC.PM4L == 0x01)) { CreateBitField (BUF0, \_SB.PCI0._Y06._RW, D8RW) // _RW_: Read-Write Status D8RW = Zero } If (^MCHC.PM4H) { CreateDWordField (BUF0, \_SB.PCI0._Y07._LEN, DCLN) // _LEN: Length DCLN = Zero } If ((^MCHC.PM4H == 0x01)) { CreateBitField (BUF0, \_SB.PCI0._Y07._RW, DCRW) // _RW_: Read-Write Status DCRW = Zero } If (^MCHC.PM5L) { CreateDWordField (BUF0, \_SB.PCI0._Y08._LEN, E0LN) // _LEN: Length E0LN = Zero } If ((^MCHC.PM5L == 0x01)) { CreateBitField (BUF0, \_SB.PCI0._Y08._RW, E0RW) // _RW_: Read-Write Status E0RW = Zero } If (^MCHC.PM5H) { CreateDWordField (BUF0, \_SB.PCI0._Y09._LEN, E4LN) // _LEN: Length E4LN = Zero } If ((^MCHC.PM5H == 0x01)) { CreateBitField (BUF0, \_SB.PCI0._Y09._RW, E4RW) // _RW_: Read-Write Status E4RW = Zero } If (^MCHC.PM6L) { CreateDWordField (BUF0, \_SB.PCI0._Y0A._LEN, E8LN) // _LEN: Length E8LN = Zero } If ((^MCHC.PM6L == 0x01)) { CreateBitField (BUF0, \_SB.PCI0._Y0A._RW, E8RW) // _RW_: Read-Write Status E8RW = Zero } If (^MCHC.PM6H) { CreateDWordField (BUF0, \_SB.PCI0._Y0B._LEN, ECLN) // _LEN: Length ECLN = Zero } If ((^MCHC.PM6H == 0x01)) { CreateBitField (BUF0, \_SB.PCI0._Y0B._RW, ECRW) // _RW_: Read-Write Status ECRW = Zero } If (^MCHC.PM0H) { CreateDWordField (BUF0, \_SB.PCI0._Y0C._LEN, F0LN) // _LEN: Length F0LN = Zero } If ((^MCHC.PM0H == 0x01)) { CreateBitField (BUF0, \_SB.PCI0._Y0C._RW, F0RW) // _RW_: Read-Write Status F0RW = Zero } CreateDWordField (BUF0, \_SB.PCI0._Y0D._MIN, M1MN) // _MIN: Minimum Base Address CreateDWordField (BUF0, \_SB.PCI0._Y0D._MAX, M1MX) // _MAX: Maximum Base Address CreateDWordField (BUF0, \_SB.PCI0._Y0D._LEN, M1LN) // _LEN: Length M1MN = (^MCHC.TLUD << 0x14) M1LN = ((M1MX - M1MN) + 0x01) Return (BUF0) /* \_SB_.PCI0.BUF0 */ } Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { CreateDWordField (Arg3, 0x00, CDW1) If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) { If ((Arg2 >= 0x03)) { Name (SUPP, 0x00) Name (CTRL, 0x00) Local0 = 0x03 CreateDWordField (Arg3, 0x04, CDW2) CreateDWordField (Arg3, 0x08, CDW3) SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */ CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ CTRL &= 0x1D If (((SUPP & 0x16) != 0x16)) { CTRL &= 0x1E } If (!(CDW1 & 0x01)) { If ((CTRL & 0x01)) { Local0 &= 0x0E } If ((CTRL & 0x04)) { Local0 &= 0x0D \_SB.PCI0.LPCB.GPMD (0x00) } If ((CTRL & 0x10)) { Debug = "PCI0._OSC PCI-E cap bit set" } \_SB.PCI0.RP04.SMPC (Local0) \_SB.PCI0.RP05.SMPC (Local0) \_SB.PCI0.RP06.SMPC (Local0) } If ((Arg1 != One)) { CDW1 |= 0x08 } If ((CDW3 != CTRL)) { CDW1 |= 0x10 } CDW3 = CTRL /* \_SB_.PCI0._OSC.CTRL */ } Else { CDW1 |= 0x02 } } Else { CDW1 |= 0x04 } Return (Arg3) } Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (GPIC) { Return (Package (0x13) { Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x10 }, Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x10 }, Package (0x04) { 0x001AFFFF, 0x00, 0x00, 0x14 }, Package (0x04) { 0x001AFFFF, 0x01, 0x00, 0x10 }, Package (0x04) { 0x001AFFFF, 0x02, 0x00, 0x15 }, Package (0x04) { 0x001BFFFF, 0x00, 0x00, 0x14 }, Package (0x04) { 0x001CFFFF, 0x00, 0x00, 0x10 }, Package (0x04) { 0x001CFFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0x001CFFFF, 0x02, 0x00, 0x12 }, Package (0x04) { 0x001CFFFF, 0x03, 0x00, 0x13 }, Package (0x04) { 0x001DFFFF, 0x00, 0x00, 0x10 }, Package (0x04) { 0x001DFFFF, 0x01, 0x00, 0x12 }, Package (0x04) { 0x001DFFFF, 0x02, 0x00, 0x15 }, Package (0x04) { 0x001DFFFF, 0x03, 0x00, 0x14 }, Package (0x04) { 0x001FFFFF, 0x00, 0x00, 0x15 }, Package (0x04) { 0x001FFFFF, 0x01, 0x00, 0x12 }, Package (0x04) { 0x001FFFFF, 0x02, 0x00, 0x14 }, Package (0x04) { 0x001FFFFF, 0x03, 0x00, 0x10 } }) } Else { Return (Package (0x13) { Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 }, Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 }, Package (0x04) { 0x0007FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 }, Package (0x04) { 0x001AFFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 }, Package (0x04) { 0x001AFFFF, 0x01, \_SB.PCI0.LPCB.LNKA, 0x00 }, Package (0x04) { 0x001AFFFF, 0x02, \_SB.PCI0.LPCB.LNKF, 0x00 }, Package (0x04) { 0x001BFFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 }, Package (0x04) { 0x001CFFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 }, Package (0x04) { 0x001CFFFF, 0x01, \_SB.PCI0.LPCB.LNKB, 0x00 }, Package (0x04) { 0x001CFFFF, 0x02, \_SB.PCI0.LPCB.LNKC, 0x00 }, Package (0x04) { 0x001CFFFF, 0x03, \_SB.PCI0.LPCB.LNKD, 0x00 }, Package (0x04) { 0x001DFFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 }, Package (0x04) { 0x001DFFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 }, Package (0x04) { 0x001DFFFF, 0x02, \_SB.PCI0.LPCB.LNKF, 0x00 }, Package (0x04) { 0x001DFFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 }, Package (0x04) { 0x001FFFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 }, Package (0x04) { 0x001FFFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 }, Package (0x04) { 0x001FFFFF, 0x02, \_SB.PCI0.LPCB.LNKE, 0x00 }, Package (0x04) { 0x001FFFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 } }) } } Device (PDRC) { Name (_HID, EisaId ("PNP0C02") /* PNP Motherboard Resources */) // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Name (BUF0, ResourceTemplate () { Memory32Fixed (ReadWrite, 0x00000000, // Address Base 0x00004000, // Address Length _Y0E) Memory32Fixed (ReadWrite, 0x00000000, // Address Base 0x00004000, // Address Length _Y0F) Memory32Fixed (ReadWrite, 0x00000000, // Address Base 0x00001000, // Address Length _Y10) Memory32Fixed (ReadWrite, 0x00000000, // Address Base 0x00001000, // Address Length _Y11) Memory32Fixed (ReadWrite, 0x00000000, // Address Base 0x00000000, // Address Length _Y12) Memory32Fixed (ReadWrite, 0xFED20000, // Address Base 0x00020000, // Address Length ) Memory32Fixed (ReadWrite, 0xFED45000, // Address Base 0x0004B000, // Address Length ) }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { CreateDWordField (BUF0, \_SB.PCI0.PDRC._Y0E._BAS, RBR0) // _BAS: Base Address RBR0 = (\_SB.PCI0.LPCB.RCBA << 0x0E) CreateDWordField (BUF0, \_SB.PCI0.PDRC._Y0F._BAS, MBR0) // _BAS: Base Address MBR0 = (\_SB.PCI0.MCHC.MHBR << 0x0E) CreateDWordField (BUF0, \_SB.PCI0.PDRC._Y10._BAS, DBR0) // _BAS: Base Address DBR0 = (\_SB.PCI0.MCHC.DIBR << 0x0C) CreateDWordField (BUF0, \_SB.PCI0.PDRC._Y11._BAS, EBR0) // _BAS: Base Address EBR0 = (\_SB.PCI0.MCHC.EPBR << 0x0C) CreateDWordField (BUF0, \_SB.PCI0.PDRC._Y12._BAS, XBR0) // _BAS: Base Address XBR0 = (\_SB.PCI0.MCHC.PXBR << 0x1A) CreateDWordField (BUF0, \_SB.PCI0.PDRC._Y12._LEN, XSZ0) // _LEN: Length XSZ0 = (0x10000000 >> \_SB.PCI0.MCHC.PXSZ) Return (BUF0) /* \_SB_.PCI0.PDRC.BUF0 */ } } Device (PEGP) { Name (_ADR, 0x00010000) // _ADR: Address Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (GPIC) { Return (Package (0x04) { Package (0x04) { 0xFFFF, 0x00, 0x00, 0x10 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0xFFFF, 0x02, 0x00, 0x12 }, Package (0x04) { 0xFFFF, 0x03, 0x00, 0x13 } }) } Else { Return (Package (0x04) { Package (0x04) { 0xFFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 }, Package (0x04) { 0xFFFF, 0x01, \_SB.PCI0.LPCB.LNKB, 0x00 }, Package (0x04) { 0xFFFF, 0x02, \_SB.PCI0.LPCB.LNKC, 0x00 }, Package (0x04) { 0xFFFF, 0x03, \_SB.PCI0.LPCB.LNKD, 0x00 } }) } } Device (GFX0) { Name (_ADR, 0x00) // _ADR: Address Method (_DOS, 1, NotSerialized) // _DOS: Disable Output Switching { DSEN = (Arg0 & 0x03) } Method (_DOD, 0, NotSerialized) // _DOD: Display Output Devices { Return (Package (0x03) { 0x80010400, 0x80010200, 0x80010300 }) } Method (DSS, 1, NotSerialized) { If (((Arg0 & 0xC0000000) == 0x80000000)) { If ((NSTE & 0x03)) { NSTE &= 0xFFFD /* \NSTE */ } If ((NSTE & 0x01)) { GP37 = 0x01 } Else { GP37 = 0x00 } CSTE = NSTE /* \NSTE */ } } Device (LCD) { Method (_ADR, 0, Serialized) // _ADR: Address { Return (0x0400) } Method (_DCS, 0, NotSerialized) // _DCS: Display Current Status { Return (0x1F) } Method (_DGS, 0, NotSerialized) // _DGS: Display Graphics State { Return (0x01) } } Device (VGA) { Method (_ADR, 0, Serialized) // _ADR: Address { Return (0x0300) } Method (_DCS, 0, NotSerialized) // _DCS: Display Current Status { If ((CSTE & 0x01)) { Return (0x1F) } Return (0x1D) } Method (_DGS, 0, NotSerialized) // _DGS: Display Graphics State { If ((NSTE & 0x01)) { Return (0x01) } Return (0x00) } Method (_DSS, 1, NotSerialized) // _DSS: Device Set State { If ((Arg0 & 0x01)) { NSTE |= 0x01 /* \NSTE */ } Else { NSTE &= 0xFFFE /* \NSTE */ } DSS (Arg0) } } Device (TV) { Method (_ADR, 0, Serialized) // _ADR: Address { Return (0x0200) } Method (_DCS, 0, NotSerialized) // _DCS: Display Current Status { If ((CSTE & 0x02)) { Return (0x1F) } Return (0x1D) } Method (_DGS, 0, NotSerialized) // _DGS: Display Graphics State { If ((NSTE & 0x02)) { Return (0x01) } Return (0x00) } Method (_DSS, 1, NotSerialized) // _DSS: Device Set State { If ((Arg0 & 0x01)) { NSTE |= 0x02 /* \NSTE */ } Else { NSTE &= 0xFFFD /* \NSTE */ } DSS (Arg0) } } } } Device (HDEF) { Name (_ADR, 0x001B0000) // _ADR: Address } Device (RP04) { Name (_ADR, 0x001C0003) // _ADR: Address OperationRegion (P4CS, PCI_Config, 0x40, 0xC0) Field (P4CS, AnyAcc, NoLock, WriteAsZeros) { Offset (0x12), , 13, LAS4, 1, Offset (0x1A), ABP4, 1, , 2, PDC4, 1, , 2, PDS4, 1, Offset (0x1B), LSC4, 1, Offset (0x20), Offset (0x22), PSP4, 1, Offset (0x9C), , 30, HPS4, 1, PMS4, 1 } OperationRegion (P4CE, PCI_Config, 0xD8, 0x04) Field (P4CE, AnyAcc, NoLock, Preserve) { , 30, MPCE, 2 } Device (FRWR) { Name (_ADR, 0x00) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x09, 0x03 }) Name (_GPE, 0x11) // _GPE: General Purpose Events } Method (SMPC, 1, NotSerialized) { If ((RP4D == 0x00)) { MPCE = (Arg0 & 0x03) If (!(Arg0 & 0x01)) { ABP4 = One PDC4 = One } } } Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (\GPIC) { Return (Package (0x04) { Package (0x04) { 0xFFFF, 0x00, 0x00, 0x13 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 0x10 }, Package (0x04) { 0xFFFF, 0x02, 0x00, 0x11 }, Package (0x04) { 0xFFFF, 0x03, 0x00, 0x12 } }) } Else { Return (Package (0x04) { Package (0x04) { 0xFFFF, 0x00, \_SB.PCI0.LPCB.LNKD, 0x00 }, Package (0x04) { 0xFFFF, 0x01, \_SB.PCI0.LPCB.LNKA, 0x00 }, Package (0x04) { 0xFFFF, 0x02, \_SB.PCI0.LPCB.LNKB, 0x00 }, Package (0x04) { 0xFFFF, 0x03, \_SB.PCI0.LPCB.LNKC, 0x00 } }) } } } Device (RP05) { Name (_ADR, 0x001C0004) // _ADR: Address OperationRegion (P5CS, PCI_Config, 0x40, 0x0100) Field (P5CS, AnyAcc, NoLock, WriteAsZeros) { SBSR, 1, Offset (0x12), , 13, LAS5, 1, Offset (0x1A), ABP5, 1, , 2, PDC5, 1, , 2, PDS5, 1, Offset (0x1B), LSC5, 1, Offset (0x20), Offset (0x22), PSP5, 1, Offset (0x9C), , 30, HPS5, 1, PMS5, 1 } OperationRegion (P5CE, PCI_Config, 0xD8, 0x04) Field (P5CE, AnyAcc, NoLock, Preserve) { , 30, MPCE, 2 } Device (ARPT) { Name (_ADR, 0x00) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x09, 0x03 }) Name (_SUN, 0x05) // _SUN: Slot User Number Name (_EJD, "\\_SB.PCI0.EHC1.HUB1.PRT2") // _EJD: Ejection Dependent Device } Method (SMPC, 1, NotSerialized) { If ((RP5D == 0x00)) { MPCE = (Arg0 & 0x03) If (!(Arg0 & 0x01)) { ABP5 = One PDC5 = One } } } Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (\GPIC) { Return (Package (0x04) { Package (0x04) { 0xFFFF, 0x00, 0x00, 0x10 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 0x11 }, Package (0x04) { 0xFFFF, 0x02, 0x00, 0x12 }, Package (0x04) { 0xFFFF, 0x03, 0x00, 0x13 } }) } Else { Return (Package (0x04) { Package (0x04) { 0xFFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 }, Package (0x04) { 0xFFFF, 0x01, \_SB.PCI0.LPCB.LNKB, 0x00 }, Package (0x04) { 0xFFFF, 0x02, \_SB.PCI0.LPCB.LNKC, 0x00 }, Package (0x04) { 0xFFFF, 0x03, \_SB.PCI0.LPCB.LNKD, 0x00 } }) } } } Device (RP06) { Name (_ADR, 0x001C0005) // _ADR: Address OperationRegion (P6CS, PCI_Config, 0x40, 0x0100) Field (P6CS, AnyAcc, NoLock, WriteAsZeros) { Offset (0x12), , 13, LAS6, 1, Offset (0x1A), ABP6, 1, , 2, PDC6, 1, , 2, PDS6, 1, Offset (0x1B), LSC6, 1, Offset (0x20), Offset (0x22), PSP6, 1, Offset (0x9C), , 30, HPS6, 1, PMS6, 1 } OperationRegion (P6CE, PCI_Config, 0xD8, 0x04) Field (P6CE, AnyAcc, NoLock, Preserve) { , 30, MPCE, 2 } Device (GIGE) { Name (_ADR, 0x00) // _ADR: Address Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x09, 0x03 }) Method (EWOL, 1, NotSerialized) { If ((Arg0 == 0x01)) { GP9 |= 0x01 } Else { GP9 &= 0x00 } If ((Arg0 == GP9)) { Return (0x00) } Else { Return (0x01) } } } Method (SMPC, 1, NotSerialized) { If ((RP6D == 0x00)) { MPCE = (Arg0 & 0x03) If (!(Arg0 & 0x01)) { ABP6 = One PDC6 = One } } } Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (\GPIC) { Return (Package (0x04) { Package (0x04) { 0xFFFF, 0x00, 0x00, 0x11 }, Package (0x04) { 0xFFFF, 0x01, 0x00, 0x12 }, Package (0x04) { 0xFFFF, 0x02, 0x00, 0x13 }, Package (0x04) { 0xFFFF, 0x03, 0x00, 0x10 } }) } Else { Return (Package (0x04) { Package (0x04) { 0xFFFF, 0x00, \_SB.PCI0.LPCB.LNKB, 0x00 }, Package (0x04) { 0xFFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 }, Package (0x04) { 0xFFFF, 0x02, \_SB.PCI0.LPCB.LNKD, 0x00 }, Package (0x04) { 0xFFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 } }) } } } Device (UHC1) { Name (_ADR, 0x001D0000) // _ADR: Address OperationRegion (U1CS, PCI_Config, 0xC4, 0x04) Field (U1CS, DWordAcc, NoLock, Preserve) { U1EN, 2 } Device (HUB1) { Name (_ADR, 0x00) // _ADR: Address Device (PRT1) { Name (_ADR, 0x01) // _ADR: Address } Device (PRT2) { Name (_ADR, 0x02) // _ADR: Address Name (_EJD, "\\_SB.PCI0.RP05.ARPT") // _EJD: Ejection Dependent Device } } Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x03, 0x03 }) Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake { If (Arg0) { U1EN = 0x03 } Else { U1EN = 0x00 } } Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State { Return (0x03) } Method (_S4D, 0, NotSerialized) // _S4D: S4 Device State { Return (0x03) } } Device (UHC2) { Name (_ADR, 0x001D0001) // _ADR: Address OperationRegion (U2CS, PCI_Config, 0xC4, 0x04) Field (U2CS, DWordAcc, NoLock, Preserve) { U2EN, 2 } Device (HUB2) { Name (_ADR, 0x00) // _ADR: Address Device (PRT1) { Name (_ADR, 0x01) // _ADR: Address } Device (PRT2) { Name (_ADR, 0x02) // _ADR: Address } } Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x04, 0x03 }) Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake { If (Arg0) { U2EN = 0x03 } Else { U2EN = 0x00 } } Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State { Return (0x03) } Method (_S4D, 0, NotSerialized) // _S4D: S4 Device State { Return (0x03) } } Device (UHC3) { Name (_ADR, 0x001D0002) // _ADR: Address OperationRegion (U2CS, PCI_Config, 0xC4, 0x04) Field (U2CS, DWordAcc, NoLock, Preserve) { U3EN, 2 } Device (HUB3) { Name (_ADR, 0x00) // _ADR: Address Device (PRT1) { Name (_ADR, 0x01) // _ADR: Address } Device (PRT2) { Name (_ADR, 0x02) // _ADR: Address } } Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x0C, 0x03 }) Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake { If (Arg0) { U3EN = 0x03 } Else { U3EN = 0x00 } } Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State { Return (0x03) } Method (_S4D, 0, NotSerialized) // _S4D: S4 Device State { Return (0x03) } } Device (UHC4) { Name (_ADR, 0x001A0000) // _ADR: Address OperationRegion (U4CS, PCI_Config, 0xC4, 0x04) Field (U4CS, DWordAcc, NoLock, Preserve) { U4EN, 2 } Device (HUB4) { Name (_ADR, 0x00) // _ADR: Address Device (PRT1) { Name (_ADR, 0x01) // _ADR: Address } Device (PRT2) { Name (_ADR, 0x02) // _ADR: Address } } Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x0E, 0x03 }) Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake { If (Arg0) { U4EN = 0x03 } Else { U4EN = 0x00 } } Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State { Return (0x03) } Method (_S4D, 0, NotSerialized) // _S4D: S4 Device State { Return (0x03) } } Device (UHC5) { Name (_ADR, 0x001A0001) // _ADR: Address OperationRegion (U5CS, PCI_Config, 0xC4, 0x04) Field (U5CS, DWordAcc, NoLock, Preserve) { U5EN, 2 } Device (HUB5) { Name (_ADR, 0x00) // _ADR: Address Device (PRT1) { Name (_ADR, 0x01) // _ADR: Address } Device (PRT2) { Name (_ADR, 0x02) // _ADR: Address } } Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x05, 0x03 }) Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake { If (Arg0) { U5EN = 0x03 } Else { U5EN = 0x00 } } Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State { Return (0x03) } Method (_S4D, 0, NotSerialized) // _S4D: S4 Device State { Return (0x03) } } Device (EHC1) { Name (_ADR, 0x001D0007) // _ADR: Address OperationRegion (U7CS, PCI_Config, 0x54, 0x04) Field (U7CS, DWordAcc, NoLock, Preserve) { , 15, PMES, 1 } Device (HUB1) { Name (_ADR, 0x00) // _ADR: Address Device (PRT1) { Name (_ADR, 0x01) // _ADR: Address } Device (PRT2) { Name (_ADR, 0x02) // _ADR: Address Name (_EJD, "\\_SB.PCI0.RP05.ARPT") // _EJD: Ejection Dependent Device } Device (PRT3) { Name (_ADR, 0x03) // _ADR: Address } Device (PRT4) { Name (_ADR, 0x04) // _ADR: Address } Device (PRT5) { Name (_ADR, 0x05) // _ADR: Address } Device (PRT6) { Name (_ADR, 0x06) // _ADR: Address } } Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x0D, 0x03 }) Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State { Return (0x03) } Method (_S4D, 0, NotSerialized) // _S4D: S4 Device State { Return (0x03) } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Local0 = Package (0x07) { "AAPL,current-available", 0x05DC, "AAPL,current-extra", 0x03E8, "AAPL,current-in-sleep", 0x0BB8, Buffer (0x01) { 0x00 // . } } DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (EHC2) { Name (_ADR, 0x001A0007) // _ADR: Address OperationRegion (UFCS, PCI_Config, 0x54, 0x04) Field (UFCS, DWordAcc, NoLock, Preserve) { , 15, PMES, 1 } Device (HUB2) { Name (_ADR, 0x00) // _ADR: Address Device (PRT1) { Name (_ADR, 0x01) // _ADR: Address } Device (PRT2) { Name (_ADR, 0x02) // _ADR: Address } Device (PRT3) { Name (_ADR, 0x03) // _ADR: Address } Device (PRT4) { Name (_ADR, 0x04) // _ADR: Address } } Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x0D, 0x03 }) Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State { Return (0x03) } Method (_S4D, 0, NotSerialized) // _S4D: S4 Device State { Return (0x03) } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { Local0 = Package (0x07) { "AAPL,current-available", 0x05DC, "AAPL,current-extra", 0x03E8, "AAPL,current-in-sleep", 0x0BB8, Buffer (0x01) { 0x00 // . } } DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (LPCB) { Name (_ADR, 0x001F0000) // _ADR: Address OperationRegion (LPC0, PCI_Config, 0x40, 0xC0) Field (LPC0, AnyAcc, NoLock, Preserve) { Offset (0x20), PARC, 8, PBRC, 8, PCRC, 8, PDRC, 8, Offset (0x28), PERC, 8, PFRC, 8, PGRC, 8, PHRC, 8, Offset (0x40), IOD0, 8, IOD1, 8, Offset (0x60), , 10, XPME, 1, Offset (0xB0), RAEN, 1, , 13, RCBA, 18 } Method (GPMD, 1, NotSerialized) { XPME = Arg0 } Device (LNKA) { Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, 0x01) // _UID: Unique ID Method (_DIS, 0, Serialized) // _DIS: Disable Device { PARC = 0x80 } Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { IRQ (Level, ActiveLow, Shared, ) {1,3,4,5,6,7,10,12,14,15} }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Name (RTLA, ResourceTemplate () { IRQ (Level, ActiveLow, Shared, _Y13) {} }) CreateWordField (RTLA, \_SB.PCI0.LPCB.LNKA._CRS._Y13._INT, IRQ0) // _INT: Interrupts IRQ0 = Zero IRQ0 = (0x01 << (PARC & 0x0F)) Return (RTLA) /* \_SB_.PCI0.LPCB.LNKA._CRS.RTLA */ } Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings { CreateWordField (Arg0, 0x01, IRQ0) FindSetRightBit (IRQ0, Local0) Local0-- PARC = Local0 } Method (_STA, 0, Serialized) // _STA: Status { If ((PARC & 0x80)) { Return (0x09) } Else { Return (0x0B) } } } Device (LNKB) { Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Method (_DIS, 0, Serialized) // _DIS: Disable Device { PBRC = 0x80 } Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { IRQ (Level, ActiveLow, Shared, ) {1,3,4,5,6,7,11,12,14,15} }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Name (RTLB, ResourceTemplate () { IRQ (Level, ActiveLow, Shared, _Y14) {} }) CreateWordField (RTLB, \_SB.PCI0.LPCB.LNKB._CRS._Y14._INT, IRQ0) // _INT: Interrupts IRQ0 = Zero IRQ0 = (0x01 << (PBRC & 0x0F)) Return (RTLB) /* \_SB_.PCI0.LPCB.LNKB._CRS.RTLB */ } Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings { CreateWordField (Arg0, 0x01, IRQ0) FindSetRightBit (IRQ0, Local0) Local0-- PBRC = Local0 } Method (_STA, 0, Serialized) // _STA: Status { If ((PBRC & 0x80)) { Return (0x09) } Else { Return (0x0B) } } } Device (LNKC) { Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, 0x03) // _UID: Unique ID Method (_DIS, 0, Serialized) // _DIS: Disable Device { PCRC = 0x80 } Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { IRQ (Level, ActiveLow, Shared, ) {1,3,4,5,6,7,10,12,14,15} }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Name (RTLC, ResourceTemplate () { IRQ (Level, ActiveLow, Shared, _Y15) {} }) CreateWordField (RTLC, \_SB.PCI0.LPCB.LNKC._CRS._Y15._INT, IRQ0) // _INT: Interrupts IRQ0 = Zero IRQ0 = (0x01 << (PCRC & 0x0F)) Return (RTLC) /* \_SB_.PCI0.LPCB.LNKC._CRS.RTLC */ } Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings { CreateWordField (Arg0, 0x01, IRQ0) FindSetRightBit (IRQ0, Local0) Local0-- PCRC = Local0 } Method (_STA, 0, Serialized) // _STA: Status { If ((PCRC & 0x80)) { Return (0x09) } Else { Return (0x0B) } } } Device (LNKD) { Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, 0x04) // _UID: Unique ID Method (_DIS, 0, Serialized) // _DIS: Disable Device { PDRC = 0x80 } Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { IRQ (Level, ActiveLow, Shared, ) {1,3,4,5,6,7,11,12,14,15} }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Name (RTLD, ResourceTemplate () { IRQ (Level, ActiveLow, Shared, _Y16) {} }) CreateWordField (RTLD, \_SB.PCI0.LPCB.LNKD._CRS._Y16._INT, IRQ0) // _INT: Interrupts IRQ0 = Zero IRQ0 = (0x01 << (PDRC & 0x0F)) Return (RTLD) /* \_SB_.PCI0.LPCB.LNKD._CRS.RTLD */ } Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings { CreateWordField (Arg0, 0x01, IRQ0) FindSetRightBit (IRQ0, Local0) Local0-- PDRC = Local0 } Method (_STA, 0, Serialized) // _STA: Status { If ((PDRC & 0x80)) { Return (0x09) } Else { Return (0x0B) } } } Device (LNKE) { Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, 0x05) // _UID: Unique ID Method (_DIS, 0, Serialized) // _DIS: Disable Device { PERC = 0x80 } Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { IRQ (Level, ActiveLow, Shared, ) {1,3,4,5,6,7,10,12,14,15} }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Name (RTLE, ResourceTemplate () { IRQ (Level, ActiveLow, Shared, _Y17) {} }) CreateWordField (RTLE, \_SB.PCI0.LPCB.LNKE._CRS._Y17._INT, IRQ0) // _INT: Interrupts IRQ0 = Zero IRQ0 = (0x01 << (PERC & 0x0F)) Return (RTLE) /* \_SB_.PCI0.LPCB.LNKE._CRS.RTLE */ } Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings { CreateWordField (Arg0, 0x01, IRQ0) FindSetRightBit (IRQ0, Local0) Local0-- PERC = Local0 } Method (_STA, 0, Serialized) // _STA: Status { If ((PERC & 0x80)) { Return (0x09) } Else { Return (0x0B) } } } Device (LNKF) { Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, 0x06) // _UID: Unique ID Method (_DIS, 0, Serialized) // _DIS: Disable Device { PFRC = 0x80 } Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { IRQ (Level, ActiveLow, Shared, ) {1,3,4,5,6,7,11,12,14,15} }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Name (RTLF, ResourceTemplate () { IRQ (Level, ActiveLow, Shared, _Y18) {} }) CreateWordField (RTLF, \_SB.PCI0.LPCB.LNKF._CRS._Y18._INT, IRQ0) // _INT: Interrupts IRQ0 = Zero IRQ0 = (0x01 << (PFRC & 0x0F)) Return (RTLF) /* \_SB_.PCI0.LPCB.LNKF._CRS.RTLF */ } Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings { CreateWordField (Arg0, 0x01, IRQ0) FindSetRightBit (IRQ0, Local0) Local0-- PFRC = Local0 } Method (_STA, 0, Serialized) // _STA: Status { If ((PFRC & 0x80)) { Return (0x09) } Else { Return (0x0B) } } } Device (LNKG) { Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, 0x07) // _UID: Unique ID Method (_DIS, 0, Serialized) // _DIS: Disable Device { PGRC = 0x80 } Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { IRQ (Level, ActiveLow, Shared, ) {1,3,4,5,6,7,10,12,14,15} }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Name (RTLG, ResourceTemplate () { IRQ (Level, ActiveLow, Shared, _Y19) {} }) CreateWordField (RTLG, \_SB.PCI0.LPCB.LNKG._CRS._Y19._INT, IRQ0) // _INT: Interrupts IRQ0 = Zero IRQ0 = (0x01 << (PGRC & 0x0F)) Return (RTLG) /* \_SB_.PCI0.LPCB.LNKG._CRS.RTLG */ } Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings { CreateWordField (Arg0, 0x01, IRQ0) FindSetRightBit (IRQ0, Local0) Local0-- PGRC = Local0 } Method (_STA, 0, Serialized) // _STA: Status { If ((PGRC & 0x80)) { Return (0x09) } Else { Return (0x0B) } } } Device (LNKH) { Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID Name (_UID, 0x08) // _UID: Unique ID Method (_DIS, 0, Serialized) // _DIS: Disable Device { PHRC = 0x80 } Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { IRQ (Level, ActiveLow, Shared, ) {1,3,4,5,6,7,11,12,14,15} }) Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { Name (RTLH, ResourceTemplate () { IRQ (Level, ActiveLow, Shared, _Y1A) {} }) CreateWordField (RTLH, \_SB.PCI0.LPCB.LNKH._CRS._Y1A._INT, IRQ0) // _INT: Interrupts IRQ0 = Zero IRQ0 = (0x01 << (PHRC & 0x0F)) Return (RTLH) /* \_SB_.PCI0.LPCB.LNKH._CRS.RTLH */ } Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings { CreateWordField (Arg0, 0x01, IRQ0) FindSetRightBit (IRQ0, Local0) Local0-- PHRC = Local0 } Method (_STA, 0, Serialized) // _STA: Status { If ((PHRC & 0x80)) { Return (0x09) } Else { Return (0x0B) } } } Device (SMC) { Name (_HID, EisaId ("APP0001")) // _HID: Hardware ID Name (_CID, "smc-santarosa") // _CID: Compatible ID Name (_STA, 0x0B) // _STA: Status Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, 0x0300, // Range Minimum 0x0300, // Range Maximum 0x01, // Alignment 0x20, // Length ) IRQNoFlags () {6} }) } Device (EC) { Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, 0x0062, // Range Minimum 0x0062, // Range Maximum 0x00, // Alignment 0x01, // Length ) IO (Decode16, 0x0066, // Range Minimum 0x0066, // Range Maximum 0x00, // Alignment 0x01, // Length ) }) Name (_GPE, 0x17) // _GPE: General Purpose Events Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x18, 0x03 }) Name (ECOK, 0x00) OperationRegion (ECOR, EmbeddedControl, 0x00, 0xFF) Field (ECOR, ByteAcc, Lock, Preserve) { ECVS, 8, LSTE, 1, RPWR, 1, CDIN, 1, Offset (0x02), LWAK, 1, ACWK, 1, CDWK, 1, Offset (0x03), Offset (0x10), ECSS, 8, PLIM, 8, Offset (0x20), SPTR, 8, SSTS, 8, SADR, 8, SCMD, 8, SBFR, 256, SCNT, 8, SAAD, 8, SAD0, 8, SAD1, 8, SMUX, 8 } Field (ECOR, ByteAcc, Lock, Preserve) { Offset (0x24), SBDW, 16, Offset (0x46), SADW, 16 } Method (_Q5A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF { Notify (\_SB.SLPB, 0x80) // Status Change } Method (_Q80, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF { PNOT () } Method (_QCD, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF { If (CDIN) { Notify (\_SB.PCI0.PATA, 0x81) // Information Change } Else { Notify (\_SB.PCI0.PATA, 0x82) // Device-Specific Change } } Method (_REG, 2, NotSerialized) // _REG: Region Availability { ECOK = Arg1 If ((Arg1 == 0x01)) {} ECSS = 0x00 } } Device (DMAC) { Name (_HID, EisaId ("PNP0200") /* PC-class DMA Controller */) // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, 0x0000, // Range Minimum 0x0000, // Range Maximum 0x01, // Alignment 0x20, // Length ) IO (Decode16, 0x0081, // Range Minimum 0x0081, // Range Maximum 0x01, // Alignment 0x11, // Length ) IO (Decode16, 0x0093, // Range Minimum 0x0093, // Range Maximum 0x01, // Alignment 0x0D, // Length ) IO (Decode16, 0x00C0, // Range Minimum 0x00C0, // Range Maximum 0x01, // Alignment 0x20, // Length ) DMA (Compatibility, NotBusMaster, Transfer8_16, ) {4} }) } Device (FWHD) { Name (_HID, EisaId ("INT0800") /* Intel 82802 Firmware Hub Device */) // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { Memory32Fixed (ReadOnly, 0xFF000000, // Address Base 0x01000000, // Address Length ) }) } Device (HPET) { Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0C01") /* System Board */) // _CID: Compatible ID Name (BUF0, ResourceTemplate () { IRQNoFlags () {0} IRQNoFlags () {8} Memory32Fixed (ReadOnly, 0xFED00000, // Address Base 0x00000400, // Address Length _Y1B) }) Method (_STA, 0, NotSerialized) // _STA: Status { If ((OSYS >= 0x07D1)) { If (HPAE) { Return (0x0F) } } ElseIf (HPAE) { Return (0x0B) } Return (0x00) } Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings { If (HPAE) { CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET._Y1B._BAS, HPT0) // _BAS: Base Address If ((HPAS == 0x01)) { HPT0 = 0xFED01000 } If ((HPAS == 0x02)) { HPT0 = 0xFED02000 } If ((HPAS == 0x03)) { HPT0 = 0xFED03000 } } Return (BUF0) /* \_SB_.PCI0.LPCB.HPET.BUF0 */ } } Device (IPIC) { Name (_HID, EisaId ("PNP0000") /* 8259-compatible Programmable Interrupt Controller */) // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, 0x0020, // Range Minimum 0x0020, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x0024, // Range Minimum 0x0024, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x0028, // Range Minimum 0x0028, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x002C, // Range Minimum 0x002C, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x0030, // Range Minimum 0x0030, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x0034, // Range Minimum 0x0034, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x0038, // Range Minimum 0x0038, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x003C, // Range Minimum 0x003C, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x00A0, // Range Minimum 0x00A0, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x00A4, // Range Minimum 0x00A4, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x00A8, // Range Minimum 0x00A8, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x00AC, // Range Minimum 0x00AC, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x00B0, // Range Minimum 0x00B0, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x00B4, // Range Minimum 0x00B4, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x00B8, // Range Minimum 0x00B8, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x00BC, // Range Minimum 0x00BC, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x04D0, // Range Minimum 0x04D0, // Range Maximum 0x01, // Alignment 0x02, // Length ) IRQNoFlags () {2} }) } Device (MATH) { Name (_HID, EisaId ("PNP0C04") /* x87-compatible Floating Point Processing Unit */) // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, 0x00F0, // Range Minimum 0x00F0, // Range Maximum 0x01, // Alignment 0x01, // Length ) IRQNoFlags () {13} }) } Device (LDRC) { Name (_HID, EisaId ("PNP0C02") /* PNP Motherboard Resources */) // _HID: Hardware ID Name (_UID, 0x02) // _UID: Unique ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, 0x002E, // Range Minimum 0x002E, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x004E, // Range Minimum 0x004E, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x0061, // Range Minimum 0x0061, // Range Maximum 0x01, // Alignment 0x01, // Length ) IO (Decode16, 0x0063, // Range Minimum 0x0063, // Range Maximum 0x01, // Alignment 0x01, // Length ) IO (Decode16, 0x0065, // Range Minimum 0x0065, // Range Maximum 0x01, // Alignment 0x01, // Length ) IO (Decode16, 0x0067, // Range Minimum 0x0067, // Range Maximum 0x01, // Alignment 0x01, // Length ) IO (Decode16, 0x0070, // Range Minimum 0x0070, // Range Maximum 0x01, // Alignment 0x01, // Length ) IO (Decode16, 0x0080, // Range Minimum 0x0080, // Range Maximum 0x01, // Alignment 0x01, // Length ) IO (Decode16, 0x0092, // Range Minimum 0x0092, // Range Maximum 0x01, // Alignment 0x01, // Length ) IO (Decode16, 0x00B2, // Range Minimum 0x00B2, // Range Maximum 0x01, // Alignment 0x02, // Length ) IO (Decode16, 0x0680, // Range Minimum 0x0680, // Range Maximum 0x01, // Alignment 0x20, // Length ) IO (Decode16, 0x0800, // Range Minimum 0x0800, // Range Maximum 0x01, // Alignment 0x10, // Length ) IO (Decode16, 0x0810, // Range Minimum 0x0810, // Range Maximum 0x01, // Alignment 0x08, // Length ) IO (Decode16, 0x0400, // Range Minimum 0x0400, // Range Maximum 0x01, // Alignment 0x80, // Length ) IO (Decode16, 0x0500, // Range Minimum 0x0500, // Range Maximum 0x01, // Alignment 0x40, // Length ) IO (Decode16, 0x1640, // Range Minimum 0x1640, // Range Maximum 0x01, // Alignment 0x10, // Length ) }) } Device (RTC) { Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, 0x0070, // Range Minimum 0x0070, // Range Maximum 0x01, // Alignment 0x08, // Length ) }) } Device (TIMR) { Name (_HID, EisaId ("PNP0100") /* PC-class System Timer */) // _HID: Hardware ID Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { IO (Decode16, 0x0040, // Range Minimum 0x0040, // Range Maximum 0x01, // Alignment 0x04, // Length ) IO (Decode16, 0x0050, // Range Minimum 0x0050, // Range Maximum 0x10, // Alignment 0x04, // Length ) }) } } Device (PATA) { Name (_ADR, 0x001F0001) // _ADR: Address OperationRegion (PACS, PCI_Config, 0x40, 0xC0) Field (PACS, DWordAcc, NoLock, Preserve) { PRIT, 16, Offset (0x04), PSIT, 4, Offset (0x08), SYNC, 4, Offset (0x0A), SDT0, 2, , 2, SDT1, 2, Offset (0x14), ICR0, 4, ICR1, 4, ICR2, 4, ICR3, 4, ICR4, 4, ICR5, 4 } Device (PRID) { Name (_ADR, 0x00) // _ADR: Address Method (_GTM, 0, NotSerialized) // _GTM: Get Timing Mode { Name (PBUF, Buffer (0x14) { /* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ /* 0010 */ 0x00, 0x00, 0x00, 0x00 // .... }) CreateDWordField (PBUF, 0x00, PIO0) CreateDWordField (PBUF, 0x04, DMA0) CreateDWordField (PBUF, 0x08, PIO1) CreateDWordField (PBUF, 0x0C, DMA1) CreateDWordField (PBUF, 0x10, FLAG) PIO0 = GETP (PRIT) DMA0 = GDMA ((SYNC & 0x01), (ICR3 & 0x01), ( ICR0 & 0x01), SDT0, (ICR1 & 0x01)) If ((DMA0 == 0xFFFFFFFF)) { DMA0 = PIO0 /* \_SB_.PCI0.PATA.PRID._GTM.PIO0 */ } If ((PRIT & 0x4000)) { If (((PRIT & 0x90) == 0x80)) { PIO1 = 0x0384 } Else { PIO1 = GETT (PSIT) } } Else { PIO1 = 0xFFFFFFFF } DMA1 = GDMA ((SYNC & 0x02), (ICR3 & 0x02), ( ICR0 & 0x02), SDT1, (ICR1 & 0x02)) If ((DMA1 == 0xFFFFFFFF)) { DMA1 = PIO1 /* \_SB_.PCI0.PATA.PRID._GTM.PIO1 */ } FLAG = GETF ((SYNC & 0x01), (SYNC & 0x02), PRIT) If (((PIO0 == 0xFFFFFFFF) & (DMA0 == 0xFFFFFFFF))) { PIO0 = 0x78 DMA0 = 0x14 FLAG = 0x03 } Return (PBUF) /* \_SB_.PCI0.PATA.PRID._GTM.PBUF */ } Method (_STM, 3, NotSerialized) // _STM: Set Timing Mode { CreateDWordField (Arg0, 0x00, PIO0) CreateDWordField (Arg0, 0x04, DMA0) CreateDWordField (Arg0, 0x08, PIO1) CreateDWordField (Arg0, 0x0C, DMA1) CreateDWordField (Arg0, 0x10, FLAG) If ((SizeOf (Arg1) == 0x0200)) { PRIT &= 0xC0F0 SYNC &= 0x02 SDT0 = 0x00 ICR0 &= 0x02 ICR1 &= 0x02 ICR3 &= 0x02 ICR5 &= 0x02 CreateWordField (Arg1, 0x62, W490) CreateWordField (Arg1, 0x6A, W530) CreateWordField (Arg1, 0x7E, W630) CreateWordField (Arg1, 0x80, W640) CreateWordField (Arg1, 0xB0, W880) CreateWordField (Arg1, 0xBA, W930) PRIT |= 0x8004 If (((FLAG & 0x02) && (W490 & 0x0800))) { PRIT |= 0x02 } PRIT |= SETP (PIO0, W530, W640) If ((FLAG & 0x01)) { SYNC |= 0x01 SDT0 = SDMA (DMA0) If ((DMA0 < 0x1E)) { ICR3 |= 0x01 } If ((DMA0 < 0x3C)) { ICR0 |= 0x01 } If ((W930 & 0x2000)) { ICR1 |= 0x01 } } } If ((SizeOf (Arg2) == 0x0200)) { PRIT &= 0xBF0F PSIT = 0x00 SYNC &= 0x01 SDT1 = 0x00 ICR0 &= 0x01 ICR1 &= 0x01 ICR3 &= 0x01 ICR5 &= 0x01 CreateWordField (Arg2, 0x62, W491) CreateWordField (Arg2, 0x6A, W531) CreateWordField (Arg2, 0x7E, W631) CreateWordField (Arg2, 0x80, W641) CreateWordField (Arg2, 0xB0, W881) CreateWordField (Arg2, 0xBA, W931) PRIT |= 0x8040 If (((FLAG & 0x08) && (W491 & 0x0800))) { PRIT |= 0x20 } If ((FLAG & 0x10)) { PRIT |= 0x4000 If ((PIO1 > 0xF0)) { PRIT |= 0x80 } Else { PRIT |= 0x10 PSIT = SETT (PIO1, W531, W641) } } If ((FLAG & 0x04)) { SYNC |= 0x02 SDT1 = SDMA (DMA1) If ((DMA1 < 0x1E)) { ICR3 |= 0x02 } If ((DMA1 < 0x3C)) { ICR0 |= 0x02 } If ((W931 & 0x2000)) { ICR1 |= 0x02 } } } } Device (P_D0) { Name (_ADR, 0x00) // _ADR: Address Method (_GTF, 0, NotSerialized) // _GTF: Get Task File { Name (PIB0, Buffer (0x0E) { /* 0000 */ 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF, 0x03, // ........ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF // ...... }) CreateByteField (PIB0, 0x01, PMD0) CreateByteField (PIB0, 0x08, DMD0) If ((PRIT & 0x02)) { If (((PRIT & 0x09) == 0x08)) { PMD0 = 0x08 } Else { PMD0 = 0x0A Local0 = ((PRIT & 0x0300) >> 0x08) Local1 = ((PRIT & 0x3000) >> 0x0C) Local2 = (Local0 + Local1) If ((0x03 == Local2)) { PMD0 = 0x0B } If ((0x05 == Local2)) { PMD0 = 0x0C } } } Else { PMD0 = 0x01 } If ((SYNC & 0x01)) { DMD0 = (SDT0 | 0x40) If ((ICR1 & 0x01)) { If ((ICR0 & 0x01)) { DMD0 += 0x02 } If ((ICR3 & 0x01)) { DMD0 = 0x45 } } } Else { DMD0 = (((PMD0 & 0x07) - 0x02) | 0x20) } Return (PIB0) /* \_SB_.PCI0.PATA.PRID.P_D0._GTF.PIB0 */ } } Device (P_D1) { Name (_ADR, 0x01) // _ADR: Address Method (_GTF, 0, NotSerialized) // _GTF: Get Task File { Name (PIB1, Buffer (0x0E) { /* 0000 */ 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF, 0x03, // ........ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF // ...... }) CreateByteField (PIB1, 0x01, PMD1) CreateByteField (PIB1, 0x08, DMD1) If ((PRIT & 0x20)) { If (((PRIT & 0x90) == 0x80)) { PMD1 = 0x08 } Else { Local0 = ((PSIT & 0x03) + ((PSIT & 0x0C) >> 0x02 )) If ((0x05 == Local0)) { PMD1 = 0x0C } ElseIf ((0x03 == Local0)) { PMD1 = 0x0B } Else { PMD1 = 0x0A } } } Else { PMD1 = 0x01 } If ((SYNC & 0x02)) { DMD1 = (SDT1 | 0x40) If ((ICR1 & 0x02)) { If ((ICR0 & 0x02)) { DMD1 += 0x02 } If ((ICR3 & 0x02)) { DMD1 = 0x45 } } } Else { DMD1 = (((PMD1 & 0x07) - 0x02) | 0x20) } Return (PIB1) /* \_SB_.PCI0.PATA.PRID.P_D1._GTF.PIB1 */ } } } } Device (SATA) { Name (_ADR, 0x001F0002) // _ADR: Address OperationRegion (SACS, PCI_Config, 0x40, 0xC0) Field (SACS, DWordAcc, NoLock, Preserve) { PRIT, 16, SECT, 16, PSIT, 4, SSIT, 4, Offset (0x08), SYNC, 4, Offset (0x0A), SDT0, 2, , 2, SDT1, 2, Offset (0x0B), SDT2, 2, , 2, SDT3, 2, Offset (0x14), ICR0, 4, ICR1, 4, ICR2, 4, ICR3, 4, ICR4, 4, ICR5, 4, Offset (0x50), MAPV, 2 } } Device (SBUS) { Name (_ADR, 0x001F0003) // _ADR: Address OperationRegion (SMBP, PCI_Config, 0x40, 0xC0) Field (SMBP, DWordAcc, NoLock, Preserve) { , 2, I2CE, 1 } OperationRegion (SMBE, PCI_Config, 0x04, 0x02) Field (SMBE, AnyAcc, NoLock, Preserve) { IOSE, 1 } OperationRegion (SMBI, SystemIO, 0xEFA0, 0x10) Field (SMBI, ByteAcc, NoLock, Preserve) { HSTS, 8, Offset (0x02), HCON, 8, HCOM, 8, TXSA, 8, DAT0, 8, DAT1, 8, HBDR, 8, PECR, 8, RXSA, 8, SDAT, 16 } Method (ENAB, 0, NotSerialized) { IOSE = 0x01 } Method (SSXB, 2, Serialized) { If (STRT ()) { Return (0x00) } I2CE = 0x00 HSTS = 0xBF TXSA = Arg0 HCOM = Arg1 HCON = 0x48 If (COMP ()) { HSTS |= 0xFF Return (0x01) } Return (0x00) } Method (SRXB, 1, Serialized) { If (STRT ()) { Return (0xFFFF) } I2CE = 0x00 HSTS = 0xBF TXSA = (Arg0 | 0x01) HCON = 0x44 If (COMP ()) { HSTS |= 0xFF Return (DAT0) /* \_SB_.PCI0.SBUS.DAT0 */ } Return (0xFFFF) } Method (SWRB, 3, Serialized) { If (STRT ()) { Return (0x00) } I2CE = 0x00 HSTS = 0xBF TXSA = Arg0 HCOM = Arg1 DAT0 = Arg2 HCON = 0x48 If (COMP ()) { HSTS |= 0xFF Return (0x01) } Return (0x00) } Method (SRDB, 2, Serialized) { If (STRT ()) { Return (0xFFFF) } I2CE = 0x00 HSTS = 0xBF TXSA = (Arg0 | 0x01) HCOM = Arg1 HCON = 0x48 If (COMP ()) { HSTS |= 0xFF Return (DAT0) /* \_SB_.PCI0.SBUS.DAT0 */ } Return (0xFFFF) } Method (SBLW, 4, Serialized) { If (STRT ()) { Return (0x00) } I2CE = Arg3 HSTS = 0xBF TXSA = Arg0 HCOM = Arg1 DAT0 = SizeOf (Arg2) Local1 = 0x00 HBDR = DerefOf (Arg2 [0x00]) HCON = 0x54 While ((SizeOf (Arg2) > Local1)) { Local0 = 0x0FA0 While ((!(HSTS & 0x80) && Local0)) { Local0-- Stall (0x32) } If (!Local0) { KILL () Return (0x00) } HSTS = 0x80 Local1++ If ((SizeOf (Arg2) > Local1)) { HBDR = DerefOf (Arg2 [Local1]) } } If (COMP ()) { HSTS |= 0xFF Return (0x01) } Return (0x00) } Method (SBLR, 3, Serialized) { Name (TBUF, Buffer (0x0100) {}) If (STRT ()) { Return (0x00) } I2CE = Arg2 HSTS = 0xBF TXSA = (Arg0 | 0x01) HCOM = Arg1 HCON = 0x54 Local0 = 0x0FA0 While ((!(HSTS & 0x80) && Local0)) { Local0-- Stall (0x32) } If (!Local0) { KILL () Return (0x00) } TBUF [0x00] = DAT0 /* \_SB_.PCI0.SBUS.DAT0 */ HSTS = 0x80 Local1 = 0x01 While ((Local1 < DerefOf (TBUF [0x00]))) { Local0 = 0x0FA0 While ((!(HSTS & 0x80) && Local0)) { Local0-- Stall (0x32) } If (!Local0) { KILL () Return (0x00) } TBUF [Local1] = HBDR /* \_SB_.PCI0.SBUS.HBDR */ HSTS = 0x80 Local1++ } If (COMP ()) { HSTS |= 0xFF Return (TBUF) /* \_SB_.PCI0.SBUS.SBLR.TBUF */ } Return (0x00) } Method (STRT, 0, Serialized) { Local0 = 0xC8 While (Local0) { If ((HSTS & 0x40)) { Local0-- Sleep (0x01) If ((Local0 == 0x00)) { Return (0x01) } } Else { Local0 = 0x00 } } Local0 = 0x0FA0 While (Local0) { If ((HSTS & 0x01)) { Local0-- Stall (0x32) If ((Local0 == 0x00)) { KILL () } } Else { Return (0x00) } } Return (0x01) } Method (COMP, 0, Serialized) { Local0 = 0x0FA0 While (Local0) { If ((HSTS & 0x02)) { Return (0x01) } Else { Local0-- Stall (0x32) If ((Local0 == 0x00)) { KILL () } } } Return (0x00) } Method (KILL, 0, Serialized) { HCON |= 0x02 HSTS |= 0xFF } } } } } ECDT ---- [000h 0000 4] Signature : "ECDT" [Embedded Controller Boot Resources Table] [004h 0004 4] Table Length : 00000053 [008h 0008 1] Revision : 01 [009h 0009 1] Checksum : 39 [00Ah 0010 6] Oem ID : "APPLE " [010h 0016 8] Oem Table ID : "Apple00" [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "Loki" [020h 0032 4] Asl Compiler Revision : 0000005F [024h 0036 12] Command/Status Register : [Generic Address Structure] [024h 0036 1] Space ID : 01 [SystemIO] [025h 0037 1] Bit Width : 08 [026h 0038 1] Bit Offset : 00 [027h 0039 1] Encoded Access Width : 00 [Undefined/Legacy] [028h 0040 8] Address : 0000000000000066 [030h 0048 12] Data Register : [Generic Address Structure] [030h 0048 1] Space ID : 01 [SystemIO] [031h 0049 1] Bit Width : 08 [032h 0050 1] Bit Offset : 00 [033h 0051 1] Encoded Access Width : 00 [Undefined/Legacy] [034h 0052 8] Address : 0000000000000062 [03Ch 0060 4] UID : 00000000 [040h 0064 1] GPE Number : 17 [041h 0065 18] Namepath : "\_SB.PCI0.LPCB.EC" Raw Table Data: Length 83 (0x53) 0000: 45 43 44 54 53 00 00 00 01 39 41 50 50 4C 45 20 // ECDTS....9APPLE 0010: 41 70 70 6C 65 30 30 00 01 00 00 00 4C 6F 6B 69 // Apple00.....Loki 0020: 5F 00 00 00 01 08 00 00 66 00 00 00 00 00 00 00 // _.......f....... 0030: 01 08 00 00 62 00 00 00 00 00 00 00 00 00 00 00 // ....b........... 0040: 17 5C 5F 53 42 2E 50 43 49 30 2E 4C 50 43 42 2E // .\_SB.PCI0.LPCB. 0050: 45 43 00 // EC. FACP ---- [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 000000F4 [008h 0008 1] Revision : 03 [009h 0009 1] Checksum : 78 [00Ah 0010 6] Oem ID : "APPLE " [010h 0016 8] Oem Table ID : "Apple00" [018h 0024 4] Oem Revision : 000000C1 [01Ch 0028 4] Asl Compiler ID : "Loki" [020h 0032 4] Asl Compiler Revision : 0000005F [024h 0036 4] FACS Address : BFECC000 [028h 0040 4] DSDT Address : BFEE2000 [02Ch 0044 1] Model : 00 [02Dh 0045 1] PM Profile : 01 [Desktop] [02Eh 0046 2] SCI Interrupt : 0009 [030h 0048 4] SMI Command Port : 000000B2 [034h 0052 1] ACPI Enable Value : F0 [035h 0053 1] ACPI Disable Value : F1 [036h 0054 1] S4BIOS Command : F2 [037h 0055 1] P-State Control : 80 [038h 0056 4] PM1A Event Block Address : 00000400 [03Ch 0060 4] PM1B Event Block Address : 00000000 [040h 0064 4] PM1A Control Block Address : 00000404 [044h 0068 4] PM1B Control Block Address : 00000000 [048h 0072 4] PM2 Control Block Address : 00000420 [04Ch 0076 4] PM Timer Block Address : 00000408 [050h 0080 4] GPE0 Block Address : 00000428 [054h 0084 4] GPE1 Block Address : 00000000 [058h 0088 1] PM1 Event Block Length : 04 [059h 0089 1] PM1 Control Block Length : 02 [05Ah 0090 1] PM2 Control Block Length : 01 [05Bh 0091 1] PM Timer Block Length : 04 [05Ch 0092 1] GPE0 Block Length : 08 [05Dh 0093 1] GPE1 Block Length : 00 [05Eh 0094 1] GPE1 Base Offset : 10 [05Fh 0095 1] _CST Support : 00 [060h 0096 2] C2 Latency : 0065 [062h 0098 2] C3 Latency : 03E9 [064h 0100 2] CPU Cache Size : 0000 [066h 0102 2] Cache Flush Stride : 0000 [068h 0104 1] Duty Cycle Offset : 01 [069h 0105 1] Duty Cycle Width : 03 [06Ah 0106 1] RTC Day Alarm Index : 0D [06Bh 0107 1] RTC Month Alarm Index : 00 [06Ch 0108 1] RTC Century Index : 32 [06Dh 0109 2] Boot Flags (decoded below) : 0001 Legacy Devices Supported (V2) : 1 8042 Present on ports 60/64 (V2) : 0 VGA Not Present (V4) : 0 MSI Not Supported (V4) : 0 PCIe ASPM Not Supported (V4) : 0 CMOS RTC Not Present (V5) : 0 [06Fh 0111 1] Reserved : 00 [070h 0112 4] Flags (decoded below) : 000084A5 WBINVD instruction is operational (V1) : 1 WBINVD flushes all caches (V1) : 0 All CPUs support C1 (V1) : 1 C2 works on MP system (V1) : 0 Control Method Power Button (V1) : 0 Control Method Sleep Button (V1) : 1 RTC wake not in fixed reg space (V1) : 0 RTC can wake system from S4 (V1) : 1 32-bit PM Timer (V1) : 0 Docking Supported (V1) : 0 Reset Register Supported (V2) : 1 Sealed Case (V3) : 0 Headless - No Video (V3) : 0 Use native instr after SLP_TYPx (V3) : 0 PCIEXP_WAK Bits Supported (V4) : 0 Use Platform Timer (V4) : 1 RTC_STS valid on S4 wake (V4) : 0 Remote Power-on capable (V4) : 0 Use APIC Cluster Model (V4) : 0 Use APIC Physical Destination Mode (V4) : 0 Hardware Reduced (V5) : 0 Low Power S0 Idle (V5) : 0 [074h 0116 12] Reset Register : [Generic Address Structure] [074h 0116 1] Space ID : 01 [SystemIO] [075h 0117 1] Bit Width : 08 [076h 0118 1] Bit Offset : 00 [077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] [078h 0120 8] Address : 0000000000000CF9 [080h 0128 1] Value to cause reset : 06 [081h 0129 2] ARM Flags (decoded below) : 0000 PSCI Compliant : 0 Must use HVC for PSCI : 0 [083h 0131 1] FADT Minor Revision : 00 [084h 0132 8] FACS Address : 00000000BFECC000 [08Ch 0140 8] DSDT Address : 00000000BFEE2000 [094h 0148 12] PM1A Event Block : [Generic Address Structure] [094h 0148 1] Space ID : 01 [SystemIO] [095h 0149 1] Bit Width : 20 [096h 0150 1] Bit Offset : 00 [097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] [098h 0152 8] Address : 0000000000000400 [0A0h 0160 12] PM1B Event Block : [Generic Address Structure] [0A0h 0160 1] Space ID : 01 [SystemIO] [0A1h 0161 1] Bit Width : 00 [0A2h 0162 1] Bit Offset : 00 [0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] [0A4h 0164 8] Address : 0000000000000000 [0ACh 0172 12] PM1A Control Block : [Generic Address Structure] [0ACh 0172 1] Space ID : 01 [SystemIO] [0ADh 0173 1] Bit Width : 10 [0AEh 0174 1] Bit Offset : 00 [0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] [0B0h 0176 8] Address : 0000000000000404 [0B8h 0184 12] PM1B Control Block : [Generic Address Structure] [0B8h 0184 1] Space ID : 01 [SystemIO] [0B9h 0185 1] Bit Width : 00 [0BAh 0186 1] Bit Offset : 00 [0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] [0BCh 0188 8] Address : 0000000000000000 [0C4h 0196 12] PM2 Control Block : [Generic Address Structure] [0C4h 0196 1] Space ID : 01 [SystemIO] [0C5h 0197 1] Bit Width : 08 [0C6h 0198 1] Bit Offset : 00 [0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] [0C8h 0200 8] Address : 0000000000000420 [0D0h 0208 12] PM Timer Block : [Generic Address Structure] [0D0h 0208 1] Space ID : 01 [SystemIO] [0D1h 0209 1] Bit Width : 20 [0D2h 0210 1] Bit Offset : 00 [0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] [0D4h 0212 8] Address : 0000000000000408 [0DCh 0220 12] GPE0 Block : [Generic Address Structure] [0DCh 0220 1] Space ID : 01 [SystemIO] [0DDh 0221 1] Bit Width : 40 [0DEh 0222 1] Bit Offset : 00 [0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] [0E0h 0224 8] Address : 0000000000000428 [0E8h 0232 12] GPE1 Block : [Generic Address Structure] [0E8h 0232 1] Space ID : 01 [SystemIO] [0E9h 0233 1] Bit Width : 00 [0EAh 0234 1] Bit Offset : 00 [0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] [0ECh 0236 8] Address : 0000000000000000 Raw Table Data: Length 244 (0xF4) 0000: 46 41 43 50 F4 00 00 00 03 78 41 50 50 4C 45 20 // FACP.....xAPPLE 0010: 41 70 70 6C 65 30 30 00 C1 00 00 00 4C 6F 6B 69 // Apple00.....Loki 0020: 5F 00 00 00 00 C0 EC BF 00 20 EE BF 00 01 09 00 // _........ ...... 0030: B2 00 00 00 F0 F1 F2 80 00 04 00 00 00 00 00 00 // ................ 0040: 04 04 00 00 00 00 00 00 20 04 00 00 08 04 00 00 // ........ ....... 0050: 28 04 00 00 00 00 00 00 04 02 01 04 08 00 10 00 // (............... 0060: 65 00 E9 03 00 00 00 00 01 03 0D 00 32 01 00 00 // e...........2... 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ 0080: 06 00 00 00 00 C0 EC BF 00 00 00 00 00 20 EE BF // ............. .. 0090: 00 00 00 00 01 20 00 00 00 04 00 00 00 00 00 00 // ..... .......... 00A0: 01 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ 00B0: 04 04 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // ................ 00C0: 00 00 00 00 01 08 00 00 20 04 00 00 00 00 00 00 // ........ ....... 00D0: 01 20 00 00 08 04 00 00 00 00 00 00 01 40 00 00 // . ...........@.. 00E0: 28 04 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // (............... 00F0: 00 00 00 00 // .... FACS ---- [000h 0000 4] Signature : "FACS" [004h 0004 4] Length : 00000040 [008h 0008 4] Hardware Signature : 00001000 [00Ch 0012 4] 32 Firmware Waking Vector : 00000000 [010h 0016 4] Global Lock : 00000000 [014h 0020 4] Flags (decoded below) : 00000000 S4BIOS Support Present : 0 64-bit Wake Supported (V2) : 0 [018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 [020h 0032 1] Version : 01 [021h 0033 3] Reserved : 000000 [024h 0036 4] OspmFlags (decoded below) : 00000000 64-bit Wake Env Required (V2) : 0 Raw Table Data: Length 64 (0x40) 0000: 46 41 43 53 40 00 00 00 00 10 00 00 00 00 00 00 // FACS@........... 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ HPET ---- [000h 0000 4] Signature : "HPET" [High Precision Event Timer table] [004h 0004 4] Table Length : 00000038 [008h 0008 1] Revision : 01 [009h 0009 1] Checksum : CC [00Ah 0010 6] Oem ID : "APPLE " [010h 0016 8] Oem Table ID : "Apple00" [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "Loki" [020h 0032 4] Asl Compiler Revision : 0000005F [024h 0036 4] Hardware Block ID : 8086A201 [028h 0040 12] Timer Block Register : [Generic Address Structure] [028h 0040 1] Space ID : 00 [SystemMemory] [029h 0041 1] Bit Width : 00 [02Ah 0042 1] Bit Offset : 00 [02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] [02Ch 0044 8] Address : 00000000FED00000 [034h 0052 1] Sequence Number : 00 [035h 0053 2] Minimum Clock Ticks : 0080 [037h 0055 1] Flags (decoded below) : 00 4K Page Protect : 0 64K Page Protect : 0 Raw Table Data: Length 56 (0x38) 0000: 48 50 45 54 38 00 00 00 01 CC 41 50 50 4C 45 20 // HPET8.....APPLE 0010: 41 70 70 6C 65 30 30 00 01 00 00 00 4C 6F 6B 69 // Apple00.....Loki 0020: 5F 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // _............... 0030: 00 00 00 00 00 80 00 00 // ........ MCFG ---- [000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] [004h 0004 4] Table Length : 0000003C [008h 0008 1] Revision : 01 [009h 0009 1] Checksum : E4 [00Ah 0010 6] Oem ID : "APPLE " [010h 0016 8] Oem Table ID : "Apple00" [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "Loki" [020h 0032 4] Asl Compiler Revision : 0000005F [024h 0036 8] Reserved : 0000000000000000 [02Ch 0044 8] Base Address : 00000000F0000000 [034h 0052 2] Segment Group Number : 0000 [036h 0054 1] Start Bus Number : 00 [037h 0055 1] End Bus Number : FF [038h 0056 4] Reserved : 00000000 Raw Table Data: Length 60 (0x3C) 0000: 4D 43 46 47 3C 00 00 00 01 E4 41 50 50 4C 45 20 // MCFG<.....APPLE 0010: 41 70 70 6C 65 30 30 00 01 00 00 00 4C 6F 6B 69 // Apple00.....Loki 0020: 5F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 F0 // _............... 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ SBST ---- [000h 0000 4] Signature : "SBST" [Smart Battery Specification Table] [004h 0004 4] Table Length : 00000030 [008h 0008 1] Revision : 01 [009h 0009 1] Checksum : 84 [00Ah 0010 6] Oem ID : "APPLE " [010h 0016 8] Oem Table ID : "Apple00" [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "Loki" [020h 0032 4] Asl Compiler Revision : 0000005F [024h 0036 4] Warning Level : 0000001E [028h 0040 4] Low Level : 00000014 [02Ch 0044 4] Critical Level : 0000000A Raw Table Data: Length 48 (0x30) 0000: 53 42 53 54 30 00 00 00 01 84 41 50 50 4C 45 20 // SBST0.....APPLE 0010: 41 70 70 6C 65 30 30 00 01 00 00 00 4C 6F 6B 69 // Apple00.....Loki 0020: 5F 00 00 00 1E 00 00 00 14 00 00 00 0A 00 00 00 // _............... SSDT1 ----- DefinitionBlock ("", "SSDT", 1, "APPLE", "Cpu1Tst", 0x00003000) { External (_PR_.CPU0._PTC, IntObj) External (_PR_.CPU0._TSS, IntObj) External (_PR_.CPU1, DeviceObj) External (CFGD, UnknownObj) External (PDC1, UnknownObj) Scope (\_PR.CPU1) { Name (_TPC, 0x00) // _TPC: Throttling Present Capabilities Method (_PTC, 0, NotSerialized) // _PTC: Processor Throttling Control { Return (\_PR.CPU0._PTC) /* External reference */ } Method (_TSS, 0, NotSerialized) // _TSS: Throttling Supported States { Return (\_PR.CPU0._TSS) /* External reference */ } Method (_TSD, 0, NotSerialized) // _TSD: Throttling State Dependencies { If (((CFGD & 0x01000000) && !(PDC1 & 0x04))) { Return (Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00, 0xFD, 0x02 } }) } Return (Package (0x01) { Package (0x05) { 0x05, 0x00, 0x01, 0xFC, 0x01 } }) } } } SSDT2 ----- DefinitionBlock ("", "SSDT", 1, "APPLE", "CpuPm", 0x00003000) { External (_PR_.CPU0, DeviceObj) External (_PR_.CPU1, DeviceObj) Scope (\) { Name (SSDT, Package (0x0C) { "CPU0IST ", 0xBFECBC18, 0x000002BC, "CPU1IST ", 0xBFECBF18, 0x000000C8, "CPU0CST ", 0xBFECB918, 0x0000028F, "CPU1CST ", 0xBFECAF18, 0x00000085 }) Name (CFGD, 0x1D3B69F1) Name (\PDC0, 0x80000000) Name (\PDC1, 0x80000000) Name (\SDTL, 0x00) } Scope (\_PR.CPU0) { Name (HI0, 0x00) Name (HC0, 0x00) Method (_PDC, 1, NotSerialized) // _PDC: Processor Driver Capabilities { CreateDWordField (Arg0, 0x00, REVS) CreateDWordField (Arg0, 0x04, SIZE) Local0 = SizeOf (Arg0) Local1 = (Local0 - 0x08) CreateField (Arg0, 0x40, (Local1 * 0x08), TEMP) Name (STS0, Buffer (0x04) { 0x00, 0x00, 0x00, 0x00 // .... }) Concatenate (STS0, TEMP, Local2) _OSC (ToUUID ("4077a616-290c-47be-9ebd-d87058713953") /* Unknown UUID */, REVS, SIZE, Local2) } Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { CreateDWordField (Arg3, 0x00, STS0) CreateDWordField (Arg3, 0x04, CAP0) CreateDWordField (Arg0, 0x00, IID0) CreateDWordField (Arg0, 0x04, IID1) CreateDWordField (Arg0, 0x08, IID2) CreateDWordField (Arg0, 0x0C, IID3) Name (UID0, ToUUID ("4077a616-290c-47be-9ebd-d87058713953") /* Unknown UUID */) CreateDWordField (UID0, 0x00, EID0) CreateDWordField (UID0, 0x04, EID1) CreateDWordField (UID0, 0x08, EID2) CreateDWordField (UID0, 0x0C, EID3) If (!(((IID0 == EID0) && (IID1 == EID1)) && (( IID2 == EID2) && (IID3 == EID3)))) { STS0 [0x00] = 0x06 Return (Arg3) } If ((Arg1 != 0x01)) { STS0 [0x00] = 0x0A Return (Arg3) } PDC0 = ((PDC0 & 0x7FFFFFFF) | CAP0) /* \_PR_.CPU0._OSC.CAP0 */ If ((CFGD & 0x01)) { If ((((CFGD & 0x01000000) && ((PDC0 & 0x09) == 0x09)) && !(SDTL & 0x01))) { SDTL |= 0x01 OperationRegion (IST0, SystemMemory, DerefOf (SSDT [0x01]), DerefOf (SSDT [0x02])) Load (IST0, HI0) /* \_PR_.CPU0.HI0_ */ } } If ((CFGD & 0xF0)) { If ((((CFGD & 0x01000000) && (PDC0 & 0x18)) && ! (SDTL & 0x02))) { SDTL |= 0x02 OperationRegion (CST0, SystemMemory, DerefOf (SSDT [0x07]), DerefOf (SSDT [0x08])) Load (CST0, HC0) /* \_PR_.CPU0.HC0_ */ } } Return (Arg3) } } Scope (\_PR.CPU1) { Name (HI1, 0x00) Name (HC1, 0x00) Method (_PDC, 1, NotSerialized) // _PDC: Processor Driver Capabilities { CreateDWordField (Arg0, 0x00, REVS) CreateDWordField (Arg0, 0x04, SIZE) Local0 = SizeOf (Arg0) Local1 = (Local0 - 0x08) CreateField (Arg0, 0x40, (Local1 * 0x08), TEMP) Name (STS1, Buffer (0x04) { 0x00, 0x00, 0x00, 0x00 // .... }) Concatenate (STS1, TEMP, Local2) _OSC (ToUUID ("4077a616-290c-47be-9ebd-d87058713953") /* Unknown UUID */, REVS, SIZE, Local2) } Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities { CreateDWordField (Arg3, 0x00, STS1) CreateDWordField (Arg3, 0x04, CAP1) CreateDWordField (Arg0, 0x00, IID0) CreateDWordField (Arg0, 0x04, IID1) CreateDWordField (Arg0, 0x08, IID2) CreateDWordField (Arg0, 0x0C, IID3) Name (UID1, ToUUID ("4077a616-290c-47be-9ebd-d87058713953") /* Unknown UUID */) CreateDWordField (UID1, 0x00, EID0) CreateDWordField (UID1, 0x04, EID1) CreateDWordField (UID1, 0x08, EID2) CreateDWordField (UID1, 0x0C, EID3) If (!(((IID0 == EID0) && (IID1 == EID1)) && (( IID2 == EID2) && (IID3 == EID3)))) { STS1 [0x00] = 0x06 Return (Arg3) } If ((Arg1 != 0x01)) { STS1 [0x00] = 0x0A Return (Arg3) } PDC1 = ((PDC1 & 0x7FFFFFFF) | CAP1) /* \_PR_.CPU1._OSC.CAP1 */ If ((CFGD & 0x01)) { If ((((CFGD & 0x01000000) && ((PDC1 & 0x09) == 0x09)) && !(SDTL & 0x10))) { SDTL |= 0x10 OperationRegion (IST1, SystemMemory, DerefOf (SSDT [0x04]), DerefOf (SSDT [0x05])) Load (IST1, HI1) /* \_PR_.CPU1.HI1_ */ } } If ((CFGD & 0xF0)) { If ((((CFGD & 0x01000000) && (PDC1 & 0x18)) && ! (SDTL & 0x20))) { SDTL |= 0x20 OperationRegion (CST1, SystemMemory, DerefOf (SSDT [0x0A]), DerefOf (SSDT [0x0B])) Load (CST1, HC1) /* \_PR_.CPU1.HC1_ */ } } Return (Arg3) } } } SSDT3 ----- DefinitionBlock ("", "SSDT", 1, "APPLE", "Cpu0Tst", 0x00003000) { External (_PR_.CPU0, DeviceObj) External (_PSS, IntObj) External (CFGD, UnknownObj) External (PDC0, UnknownObj) Scope (\_PR.CPU0) { Name (_TPC, 0x00) // _TPC: Throttling Present Capabilities Method (_PTC, 0, NotSerialized) // _PTC: Processor Throttling Control { If ((PDC0 & 0x04)) { Return (Package (0x02) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) } }) } Return (Package (0x02) { ResourceTemplate () { Register (SystemIO, 0x04, // Bit Width 0x01, // Bit Offset 0x0000000000000410, // Address ,) }, ResourceTemplate () { Register (SystemIO, 0x04, // Bit Width 0x01, // Bit Offset 0x0000000000000410, // Address ,) } }) } Name (TSSI, Package (0x08) { Package (0x05) { 0x64, 0x03E8, 0x00, 0x00, 0x00 }, Package (0x05) { 0x58, 0x036B, 0x00, 0x0F, 0x00 }, Package (0x05) { 0x4B, 0x02EE, 0x00, 0x0E, 0x00 }, Package (0x05) { 0x3F, 0x0271, 0x00, 0x0D, 0x00 }, Package (0x05) { 0x32, 0x01F4, 0x00, 0x0C, 0x00 }, Package (0x05) { 0x26, 0x0177, 0x00, 0x0B, 0x00 }, Package (0x05) { 0x19, 0xFA, 0x00, 0x0A, 0x00 }, Package (0x05) { 0x0D, 0x7D, 0x00, 0x09, 0x00 } }) Name (TSSM, Package (0x08) { Package (0x05) { 0x64, 0x03E8, 0x00, 0x00, 0x00 }, Package (0x05) { 0x58, 0x036B, 0x00, 0x1E, 0x00 }, Package (0x05) { 0x4B, 0x02EE, 0x00, 0x1C, 0x00 }, Package (0x05) { 0x3F, 0x0271, 0x00, 0x1A, 0x00 }, Package (0x05) { 0x32, 0x01F4, 0x00, 0x18, 0x00 }, Package (0x05) { 0x26, 0x0177, 0x00, 0x16, 0x00 }, Package (0x05) { 0x19, 0xFA, 0x00, 0x14, 0x00 }, Package (0x05) { 0x0D, 0x7D, 0x00, 0x12, 0x00 } }) Name (TSSF, 0x00) Method (_TSS, 0, NotSerialized) // _TSS: Throttling Supported States { If ((!TSSF && CondRefOf (_PSS))) { Local0 = _PSS /* External reference */ Local1 = SizeOf (Local0) Local1-- Local2 = DerefOf (DerefOf (Local0 [Local1]) [0x01]) Local3 = 0x00 While ((Local3 < SizeOf (TSSI))) { Local4 = ((Local2 * (0x08 - Local3)) / 0x08) DerefOf (TSSI [Local3]) [0x01] = Local4 DerefOf (TSSM [Local3]) [0x01] = Local4 Local3++ } TSSF = Ones } If ((PDC0 & 0x04)) { Return (TSSM) /* \_PR_.CPU0.TSSM */ } Return (TSSI) /* \_PR_.CPU0.TSSI */ } Method (_TSD, 0, NotSerialized) // _TSD: Throttling State Dependencies { If (((CFGD & 0x01000000) && !(PDC0 & 0x04))) { Return (Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00, 0xFD, 0x02 } }) } Return (Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00, 0xFC, 0x01 } }) } } } SSDT4 ----- DefinitionBlock ("", "SSDT", 1, "APPLE ", "SataAhci", 0x00001000) { External (_SB_.PCI0.SATA, DeviceObj) External (GP27, UnknownObj) External (GTF0, IntObj) Scope (\_SB.PCI0.SATA) { Device (PRT0) { Name (_ADR, 0xFFFF) // _ADR: Address Method (_SDD, 1, NotSerialized) // _SDD: Set Device Data { Name (GBU0, Buffer (0x07) { 0x00, 0x00, 0x00, 0x00, 0x00, 0xA0, 0x00 // ....... }) CreateByteField (GBU0, 0x00, GB00) CreateByteField (GBU0, 0x01, GB01) CreateByteField (GBU0, 0x02, GB02) CreateByteField (GBU0, 0x03, GB03) CreateByteField (GBU0, 0x04, GB04) CreateByteField (GBU0, 0x05, GB05) CreateByteField (GBU0, 0x06, GB06) If ((SizeOf (Arg0) == 0x0200)) { CreateWordField (Arg0, 0x9C, W780) If ((W780 & 0x08)) { GB00 = 0x10 GB01 = 0x03 GB06 = 0xEF } Else { GB00 = 0x90 GB01 = 0x03 GB06 = 0xEF } } GTF0 = GBU0 /* \_SB_.PCI0.SATA.PRT0._SDD.GBU0 */ } Method (_GTF, 0, NotSerialized) // _GTF: Get Task File { Return (GTF0) /* External reference */ } Method (_PS0, 0, Serialized) // _PS0: Power State 0 { GP27 = 0x00 } Method (_PS3, 0, Serialized) // _PS3: Power State 3 { GP27 = 0x01 } Method (_PSC, 0, Serialized) // _PSC: Power State Current { If (!GP27) { Return (0x00) } Return (0x03) } } } } SSDT5 ----- DefinitionBlock ("", "SSDT", 1, "APPLE", "Cpu1Ist", 0x00003000) { External (_PR_.CPU0._PPC, IntObj) External (_PR_.CPU0._PSS, IntObj) External (_PR_.CPU1, DeviceObj) External (PDC1, UnknownObj) Scope (\_PR.CPU1) { Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilities { Return (\_PR.CPU0._PPC) /* External reference */ } Method (_PCT, 0, NotSerialized) // _PCT: Performance Control { Return (Package (0x02) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) } }) } Method (_PSS, 0, NotSerialized) // _PSS: Performance Supported States { Return (\_PR.CPU0._PSS) /* External reference */ } Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies { If ((PDC1 & 0x0800)) { Return (Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00, 0xFE, 0x02 } }) } Return (Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00, 0xFC, 0x02 } }) } } } SSDT6 ----- DefinitionBlock ("", "SSDT", 1, "APPLE", "Cpu0Ist", 0x00003000) { External (_PR_.CPU0, DeviceObj) External (CFGD, UnknownObj) External (NPSS, IntObj) External (PDC0, UnknownObj) Scope (\_PR.CPU0) { Name (_PPC, 0x00) // _PPC: Performance Present Capabilities Method (_PCT, 0, NotSerialized) // _PCT: Performance Control { If (((CFGD & 0x01) && (PDC0 & 0x01))) { Return (Package (0x02) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) } }) } Return (Package (0x02) { ResourceTemplate () { Register (SystemIO, 0x10, // Bit Width 0x00, // Bit Offset 0x0000000000000800, // Address ,) }, ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x00000000000000B3, // Address ,) } }) } Method (XPSS, 0, NotSerialized) { If ((PDC0 & 0x01)) { Return (NPSS) /* External reference */ } Return (SPSS) /* \_PR_.CPU0.SPSS */ } Name (SPSS, Package (0x06) { Package (0x06) { 0x00000A6B, 0x00006FB8, 0x0000006E, 0x0000000A, 0x00000083, 0x00000000 }, Package (0x06) { 0x00000960, 0x00006270, 0x0000006E, 0x0000000A, 0x00000183, 0x00000001 }, Package (0x06) { 0x00000855, 0x00005528, 0x0000006E, 0x0000000A, 0x00000283, 0x00000002 }, Package (0x06) { 0x0000074B, 0x000047E0, 0x0000006E, 0x0000000A, 0x00000383, 0x00000003 }, Package (0x06) { 0x00000640, 0x00003A98, 0x0000006E, 0x0000000A, 0x00000483, 0x00000004 }, Package (0x06) { 0x00000320, 0x000037DC, 0x0000006E, 0x0000000A, 0x00000583, 0x00000005 } }) Name (_PSS, Package (0x06) // _PSS: Performance Supported States { Package (0x06) { 0x00000A6B, 0x00006FB8, 0x0000000A, 0x0000000A, 0x00000A27, 0x00000A27 }, Package (0x06) { 0x00000960, 0x00006270, 0x0000000A, 0x0000000A, 0x00000925, 0x00000925 }, Package (0x06) { 0x00000855, 0x00005528, 0x0000000A, 0x0000000A, 0x00000822, 0x00000822 }, Package (0x06) { 0x0000074B, 0x000047E0, 0x0000000A, 0x0000000A, 0x00000720, 0x00000720 }, Package (0x06) { 0x00000640, 0x00003A98, 0x0000000A, 0x0000000A, 0x0000061D, 0x0000061D }, Package (0x06) { 0x00000320, 0x000037DC, 0x0000000A, 0x0000000A, 0x0000861B, 0x0000861B } }) Method (_PSD, 0, NotSerialized) // _PSD: Power State Dependencies { If ((CFGD & 0x01000000)) { If ((PDC0 & 0x0800)) { Return (Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00, 0xFE, 0x02 } }) } Return (Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00, 0xFC, 0x02 } }) } Return (Package (0x01) { Package (0x05) { 0x05, 0x00, 0x00, 0xFC, 0x01 } }) } } } SSDT7 ----- DefinitionBlock ("", "SSDT", 1, "APPLE", "Cpu1Cst", 0x00003000) { External (_PR_.CPU0._CST, IntObj) External (_PR_.CPU1, DeviceObj) External (CFGD, UnknownObj) External (PDC1, UnknownObj) Scope (\_PR.CPU1) { Method (_CST, 0, NotSerialized) // _CST: C-States { If (((CFGD & 0x01000000) && !(PDC1 & 0x10))) { Return (Package (0x02) { 0x01, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x9D, 0x03E8 } }) } Return (\_PR.CPU0._CST) /* External reference */ } } } SSDT8 ----- DefinitionBlock ("", "SSDT", 1, "APPLE", "Cpu0Cst", 0x00003001) { External (_PR_.CPU0, DeviceObj) External (CFGD, UnknownObj) External (PDC0, UnknownObj) Scope (\_PR.CPU0) { Method (ACST, 0, NotSerialized) { Return (Package (0x05) { 0x01, 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000010, // Address 0x01, // Access Size ) }, 0x02, 0x01, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000031, // Address 0x03, // Access Size ) }, 0x04, 0x39, 0x64 } }) } Method (_CST, 0, NotSerialized) // _CST: C-States { If (((CFGD & 0x01000000) && !(PDC0 & 0x10))) { Return (Package (0x02) { 0x01, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x9D, 0x03E8 } }) } If ((PDC0 & 0x0300)) { If ((CFGD & 0x80)) { Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000010, // Address ,) }, 0x02, 0x01, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000031, // Address 0x03, // Access Size ) }, 0x03, 0x39, 0x64 } }) } If ((CFGD & 0x20)) { Return (Package (0x03) { 0x02, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000010, // Address ,) }, 0x02, 0x01, 0x01F4 } }) } } If ((CFGD & 0x80)) { Return (Package (0x04) { 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000414, // Address ,) }, 0x02, 0x01, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000416, // Address ,) }, 0x03, 0x39, 0x64 } }) } If ((CFGD & 0x20)) { Return (Package (0x03) { 0x02, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x01, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (SystemIO, 0x08, // Bit Width 0x00, // Bit Offset 0x0000000000000414, // Address ,) }, 0x02, 0x01, 0x01F4 } }) } Return (Package (0x02) { 0x01, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x00, // Bit Width 0x00, // Bit Offset 0x0000000000000000, // Address ,) }, 0x01, 0x01, 0x03E8 } }) } } }